| FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256 I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval Microprocessors and Microsystems 37 (6-7), 750-757, 2013 | 65 | 2013 |
| A compact FPGA-based processor for the Secure Hash Algorithm SHA-256 R García, I Algredo-Badillo, M Morales-Sandoval, C Feregrino-Uribe, ... Computers & Electrical Engineering 40 (1), 194-202, 2014 | 58 | 2014 |
| An area/performance trade-off analysis of a GF (2m) multiplier architecture for elliptic curve cryptography M Morales-Sandoval, C Feregrino-Uribe, R Cumplido, I Algredo-Badillo Computers & Electrical Engineering 35 (1), 54-58, 2009 | 34 | 2009 |
| Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11 i standard I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval Computers & Electrical Engineering 36 (3), 565-577, 2010 | 29 | 2010 |
| A reconfigurable GF(2M) elliptic curve cryptographic coprocessor M Morales-Sandoval, C Feregrino-Uribe, R Cumplido, I Algredo-Badillo 2011 VII Southern Conference on Programmable Logic (SPL), 209-214, 2011 | 25 | 2011 |
| FPGA implementation and performance evaluation of AES-CCM cores for wireless networks I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval 2008 International Conference on Reconfigurable Computing and FPGAs, 421-426, 2008 | 25 | 2008 |
| Compact FPGA hardware architecture for public key encryption in embedded devices L Rodríguez-Flores, M Morales-Sandoval, R Cumplido, C Feregrino-Uribe, ... PloS one 13 (1), e0190939, 2018 | 23 | 2018 |
| Design and implementation of an FPGA-Based 1.452-gbps non-pipelined AES architecture I Algredo-Badillo, C Feregrino-Uribe, R Cumplido International Conference on Computational Science and Its Applications, 456-465, 2006 | 20 | 2006 |
| A metaheuristic optimization approach for parameter estimation in arrhythmia classification from unbalanced data JC Carrillo-Alarcón, LA Morales-Rosales, H Rodríguez-Rángel, ... Sensors 20 (11), 3139, 2020 | 18 | 2020 |
| Performance analysis of ANFIS in short term wind speed prediction EC Pérez, I Algredo-Badillo, VHG Rodríguez arXiv preprint arXiv:1212.2671, 2012 | 18 | 2012 |
| FPGA Implementation Cost and Performance Evaluation of the IEEE 802.16 e and IEEE 802.11 i Security Architectures Based on AES-CCM I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval 2008 5th International Conference on Electrical Engineering, Computing …, 2008 | 13 | 2008 |
| Hybrid pipeline hardware architecture based on error detection and correction for aes I Algredo-Badillo, KA Ramírez-Gutiérrez, LA Morales-Rosales, ... Sensors 21 (16), 5655, 2021 | 12 | 2021 |
| Reconfigurable arithmetic logic unit designed with threshold logic gates A Medina‐Santiago, MA Reyes‐Barranca, I Algredo‐Badillo, ... IET Circuits, Devices & Systems 13 (1), 21-30, 2019 | 12 | 2019 |
| On-road obstacle detection video system for traffic accident prevention LA Morales Rosales, I Algredo Badillo, CA Hernández Gracidas, ... Journal of Intelligent & Fuzzy Systems 35 (1), 533-547, 2018 | 12 | 2018 |
| De la Secuenciación a la Aceleración Hardware de los Programas de Alineación de ADN, una Revisión Integral D Pacheco Bautista, M González Pérez, I Algredo Badillo Revista mexicana de ingeniería biomédica 36 (3), 259-277, 2015 | 12 | 2015 |
| Karatsuba-Ofman Multiplier with Integrated Modular Reduction for (2) m GF E Cuevas-Farfan, M Morales-Sandoval, A Morales-Reyes, ... Advances in Electrical and Computer Engineering 13 (2), 1-5, 2013 | 12 | 2013 |
| Throughput and efficiency analysis of unrolled hardware architectures for the sha-512 hash algorithm I Algredo-Badillo, M Morales-Sandoval, C Feregrino-Uribe, R Cumplido 2012 IEEE Computer Society Annual Symposium on VLSI, 63-68, 2012 | 12 | 2012 |
| NFT-vehicle: A blockchain-based tokenization architecture to register transactions over a vehicle’s life cycle JC López-Pimentel, LA Morales-Rosales, I Algredo-Badillo, ... Mathematics 11 (13), 2801, 2023 | 10 | 2023 |
| An FPGA-based analysis of trade-offs in the presence of ill-conditioning and different precision levels in computations I Algredo-Badillo, JJ Conde-Mones, CA Hernández-Gracidas, ... Plos one 15 (6), e0234293, 2020 | 10 | 2020 |
| Design and implementation of a non-pipelined MD5 Hardware architecture using a new functional description I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval IEICE transactions on information and systems 91 (10), 2519-2523, 2008 | 10 | 2008 |
