| Efficient mapping of irregular C++ applications to integrated GPUs R Barik, R Kaleem, D Majeti, BT Lewis, T Shpeisman, C Hu, Y Ni, ... Proceedings of Annual IEEE/ACM International Symposium on Code Generation …, 2014 | 41 | 2014 |
| Optimization of lattice Boltzmann simulation with graphics-processing-unit parallel computing and the application in reservoir characterization C Chen, Z Wang, D Majeti, N Vrvilo, T Warburton, V Sarkar, G Li SPE Journal 21 (04), 1425-1435, 2016 | 36 | 2016 |
| Compiler-Driven Data Layout Transformation for Heterogeneous Platforms D Majeti, R Barik, J Zhao, G Max, S Vivek International Workshop on Algorithms, Models and Tools for Parallel …, 2013 | 36 | 2013 |
| Automatic data layout generation and kernel mapping for cpu+ gpu architectures D Majeti, KS Meel, R Barik, V Sarkar Proceedings of the 25th International Conference on Compiler Construction …, 2016 | 31 | 2016 |
| Extended Task Queuing: Active Messages for Heterogeneous Systems M LeBeane, B Potter, A Pan, A Dutu, V Agarwala, W Lee, D Majeti, ... SC16: International Conference for High Performance Computing, Networking …, 2016 | 20 | 2016 |
| Heterogeneous Habanero-C (H2C): a portable programming model for heterogeneous processors D Majeti, V Sarkar 2015 IEEE International Parallel and Distributed Processing Symposium …, 2015 | 20 | 2015 |
| Heterogeneous work-stealing across CPU and DSP cores V Kumar, A Sbîrlea, A Jayaraj, Z Budimlić, D Majeti, V Sarkar 2015 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2015 | 14 | 2015 |
| Low energy tree based network on chip architectures using homogeneous routers for bandwidth and latency constrained multimedia applications D Majeti, A Pasalapudi, K Yalamanchili 2009 Second International Conference on Emerging Trends in Engineering …, 2009 | 8 | 2009 |
| Design of optimal architectures using homogeneous routers for application specific network on chip K Yalamanchili, A Pasalapudi, D Majeti, V Sunitha 2008 First International Conference on Emerging Trends in Engineering and …, 2008 | 7 | 2008 |
| Adha: Automatic data layout framework for heterogeneous architectures D Majeti, KS Meel, R Barik, V Sarkar Proceedings of the 23rd international conference on Parallel architectures …, 2014 | 5 | 2014 |
| Lightweight dynamic task creation and scheduling on the Intel Single Chip Cloud (SCC) processor D Majeti Proceedings of the Fourth Workshop on Programming Language Approaches to …, 2011 | 2 | 2011 |
| Power aware work stealing MW LeBeane, D Majeti, M Breternitz US Patent 10,089,155, 2018 | | 2018 |
| Portable Programming Models for Heterogeneous Platforms D Majeti | | 2015 |
| On the arithmetic of one del Pezzo surface over the field with three elements N Kozin, D Majeti arXiv preprint arXiv:1409.7856, 2014 | | 2014 |
| Improving speculative loop parallelization via selective squash and speculation reuse SS Ananthramu, D Majeti, SK Aggarwal, M Chaudhuri Proceedings of the 19th International Conference on Parallel Architectures …, 2010 | | 2010 |
| Design of optimal architectures for application specific network on chip A Pasalapudi, D Majeti Dhirubhai Ambani Institute of Information and Communication Technology, 2008 | | 2008 |
| FPGAs (ReConFig) Additional Reviewers F Hategekimana, A Haron, A Arış, A Wild, AÉDM Martins, ... | | |
Vivek SarkarSchool of Computer Science, Georgia Institute of Technology確認したメール アドレス: gatech.edu