| Accelergy: An architecture-level energy estimation methodology for accelerator designs YN Wu, JS Emer, V Sze 2019 IEEE International Conference on Computer-Aided Design (ICCAD), 2019 | 272 | 2019 |
| Sparseloop: An analytical approach to sparse tensor accelerator modeling YN Wu, PA Tsai, A Parashar, V Sze, JS Emer 2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO …, 2022 | 64 | 2022 |
| Sparseloop: An analytical, energy-focused design space exploration methodology for sparse tensor accelerators YN Wu, PA Tsai, A Parashar, V Sze, JS Emer 2021 IEEE International Symposium on Performance Analysis of Systems and …, 2021 | 40 | 2021 |
| An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs YN Wu, V Sze, JS Emer IEEE International Symposium on Performance Analysis of Systems and Software, 2020 | 28 | 2020 |
| Highlight: Efficient and flexible dnn acceleration with hierarchical structured sparsity YN Wu, PA Tsai, S Muralidharan, A Parashar, V Sze, J Emer Proceedings of the 56th Annual IEEE/ACM International Symposium on …, 2023 | 27 | 2023 |
| Looptree: Enabling exploration of fused-layer dataflow accelerators M Gilbert, YN Wu, A Parashar, V Sze, JS Emer 2023 IEEE International Symposium on Performance Analysis of Systems and …, 2023 | 10 | 2023 |
| Sparseloop: An analytical approach to sparse tensor accelerator modeling. In 2022 55th IEEE YN Wu, PA Tsai, A Parashar, V Sze, JS Emer ACM International Symposium on Microarchitecture (MICRO), 1377-1395, 0 | 6 | |
| Tailors: Accelerating sparse tensor algebra by overbooking buffer capacity ZY Xue, YN Wu, JS Emer, V Sze Proceedings of the 56th Annual IEEE/ACM International Symposium on …, 2023 | 5 | 2023 |
| Architecture-level energy estimation for heterogeneous computing systems F Wang, YN Wu, M Woicik, JS Emer, V Sze 2021 IEEE International Symposium on Performance Analysis of Systems and …, 2021 | 4 | 2021 |
| Sparse tensor accelerators: Abstraction and modeling J Emer, A Parashar, V Sze, PA Tsai, N Wu ISCA Tutorial 2021, 2021 | 3 | 2021 |
| LoopTree: Exploring the Fused-layer Dataflow Accelerator Design Space M Gilbert, YN Wu, JS Emer, V Sze IEEE Transactions on Circuits and Systems for Artificial Intelligence, 2024 | 1 | 2024 |
| A systematic approach for architecture-level energy estimation of accelerator designs V Sze, JS Emer Massachusetts Institute of Technology, 2020 | | 2020 |
| Architecture-level Energy Estimation of Accelerator Designs YN Wu, JS Emer, V Sze Research Abstracts, 6, 2020 | | 2020 |