| 15.3 A 351TOPS/W and 372.4 GOPS compute-in-memory SRAM macro in 7nm FinFET CMOS for machine-learning applications Q Dong, ME Sinangil, B Erbagci, D Sun, WS Khwa, HJ Liao, Y Wang, ... 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 242-244, 2020 | 321 | 2020 |
| 16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications YD Chih, PH Lee, H Fujiwara, YC Shih, CF Lee, R Naous, YL Chen, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 252-254, 2021 | 302 | 2021 |
| A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous … H Fujiwara, H Mori, WC Zhao, MC Chuang, R Naous, CK Chuang, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 166 | 2022 |
| A reconfigurable 8T ultra-dynamic voltage scalable (U-DVS) SRAM in 65 nm CMOS ME Sinangil, N Verma, AP Chandrakasan IEEE Journal of Solid-State Circuits 44 (11), 3163-3173, 2009 | 156 | 2009 |
| A 7-nm compute-in-memory SRAM macro supporting multi-bit input, weight and output and achieving 351 TOPS/W and 372.4 GOPS ME Sinangil, B Erbagci, R Naous, K Akarvardar, D Sun, WS Khwa, ... IEEE Journal of Solid-State Circuits 56 (1), 188-198, 2020 | 148 | 2020 |
| Technologies for ultradynamic voltage scaling AP Chandrakasan, DC Daly, DF Finchelstein, J Kwong, YK Ramadass, ... Proceedings of the IEEE 98 (2), 191-214, 2010 | 143 | 2010 |
| Challenges and directions for low-voltage SRAM M Qazi, M Sinangil, A Chandrakasan IEEE design & test of computers 28 (1), 32-43, 2010 | 114 | 2010 |
| Self-aware computing in the Angstrom processor H Hoffmann, J Holt, G Kurian, E Lau, M Maggio, JE Miller, SM Neuman, ... Proceedings of the 49th Annual Design Automation Conference, 259-264, 2012 | 109 | 2012 |
| A 28nm high-density 6T SRAM with optimized peripheral-assist circuits for operation down to 0.6 V ME Sinangil, H Mair, AP Chandrakasan 2011 IEEE International Solid-State Circuits Conference, 260-262, 2011 | 95 | 2011 |
| Application-Specific SRAM Design Using Output Prediction to Reduce Bit-Line Switching Activity and Statistically Gated Sense Amplifiers for Up to 1.9 Lower … ME Sinangil, AP Chandrakasan IEEE Journal of Solid-State Circuits 49 (1), 107-117, 2013 | 72 | 2013 |
| System and method for performing SRAM write assist BM Zimmer, ME Sinangil US Patent 8,861,290, 2014 | 68 | 2014 |
| Cost and coding efficient motion estimation design considerations for high efficiency video coding (HEVC) standard ME Sinangil, V Sze, M Zhou, AP Chandrakasan IEEE Journal of selected topics in signal processing 7 (6), 1017-1028, 2013 | 67 | 2013 |
| A 0.7-v 1.8-mw H. 264/AVC 720p video decoder V Sze, DF Finchelstein, ME Sinangil, AP Chandrakasan IEEE Journal of Solid-State Circuits 44 (11), 2943-2956, 2009 | 63 | 2009 |
| A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination Q Dong, Z Wang, J Lim, Y Zhang, ME Sinangil, YC Shih, YD Chih, ... IEEE Journal of Solid-State Circuits 54 (1), 231-239, 2018 | 61 | 2018 |
| A 28nm 0.6 V low-power DSP for mobile applications G Gammie, N Ickes, ME Sinangil, R Rithe, J Gu, A Wang, H Mair, S Datla, ... 2011 IEEE International Solid-State Circuits Conference, 132-134, 2011 | 49 | 2011 |
| A 28 nm 2 Mbit 6 T SRAM with highly configurable low-voltage write-ability assist implementation and capacitor-based sense-amplifier input offset compensation ME Sinangil, JW Poulton, MR Fojtik, TH Greer, SG Tell, AJ Gotterba, ... IEEE Journal of Solid-State Circuits 51 (2), 557-567, 2015 | 48 | 2015 |
| A 28 nm 0.6 V low power DSP for mobile applications N Ickes, G Gammie, ME Sinangil, R Rithe, J Gu, A Wang, H Mair, S Datla, ... IEEE Journal of Solid-State Circuits 47 (1), 35-46, 2011 | 47 | 2011 |
| A reconfigurable 65nm SRAM achieving voltage scalability from 0.25–1.2 V and performance scalability from 20kHz–200MHz ME Sinangil, N Verma, AP Chandrakasan ESSCIRC 2008-34th European Solid-State Circuits Conference, 282-285, 2008 | 44 | 2008 |
| System and method for performing address-based SRAM access assists ME Sinangil, WJ Dally US Patent 9,208,900, 2015 | 42 | 2015 |
| A 45nm 0.5 V 8T column-interleaved SRAM with on-chip reference selection loop for sense-amplifier ME Sinangil, N Verma, AP Chandrakasan 2009 IEEE Asian Solid-State Circuits Conference, 225-228, 2009 | 30 | 2009 |