עקוב אחר
Jiang Hu
Jiang Hu
Professor of Electrical and Computer Engineering, Texas A&M University
כתובת אימייל מאומתת בדומיין tamu.edu - דף הבית
כותרת
צוטט על ידי
צוטט על ידי
שנה
RouteNet: Routability prediction for mixed-size designs using convolutional neural network‏
Z Xie, YH Huang, GQ Fang, H Ren, SY Fang, Y Chen, J Hu‏
2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018‏
2312018
A practical methodology for early buffer and wire resource allocation‏
CJ Alpert, J Hu, SS Sapatnekar, P Villarrubia‏
Proceedings of the 38th annual Design Automation Conference, 189-194, 2001‏
195*2001
Pattern sensitive placement perturbation for manufacturability‏
S Hu, P Shah, J Hu‏
IEEE transactions on very large scale integration (VLSI) systems 18 (6 …, 2009‏
190*2009
A timing-constrained simultaneous global routing algorithm‏
J Hu, SS Sapatnekar‏
IEEE Transactions on computer-aided design of integrated circuits and …, 2002‏
157*2002
Porosity aware buffered steiner tree construction‏
CJ Alpert, G Gandham, M Hrkić, J Hu, ST Quay‏
Proceedings of the 2003 international symposium on Physical design, 158-165, 2003‏
1452003
Joint precision optimization and high level synthesis for approximate computing‏
C Li, W Luo, SS Sapatnekar, J Hu‏
Proceedings of the 52nd annual design automation conference, 1-6, 2015‏
1432015
Steiner tree optimization for buffers, blockages, and bays‏
CJ Alpert, G Gandham, J Hu, JI Neves, ST Quay, SS Sapatnekar‏
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001‏
141*2001
A survey on multi-net global routing for integrated circuits‏
J Hu, SS Sapatnekar‏
Integration 31 (1), 1-49, 2001‏
1402001
Reducing clock skew variability via cross links‏
A Rajaram, J Hu, R Mahapatra‏
Proceedings of the 41st annual Design Automation Conference, 18-23, 2004‏
1372004
Exploring serverless computing for neural network training‏
L Feng, P Kudva, D Da Silva, J Hu‏
2018 IEEE 11th international conference on cloud computing (CLOUD), 334-341, 2018‏
1312018
Machine learning-based pre-routing timing prediction with reduced pessimism‏
EC Barboza, N Shukla, Y Chen, J Hu‏
Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019‏
1272019
A new algorithm for simultaneous gate sizing and threshold voltage assignment‏
Y Liu, J Hu‏
Proceedings of the 2009 international symposium on Physical design, 27-34, 2009‏
1172009
ALIGN: Open-source analog layout automation from the ground up‏
K Kunal, M Madhusudan, AK Sharma, W Xu, SM Burns, R Harjani, J Hu, ...‏
Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019‏
1162019
PowerNet: Transferable dynamic IR drop estimation via maximum convolutional neural network‏
Z Xie, H Ren, B Khailany, Y Sheng, S Santosh, J Hu, Y Chen‏
2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 13-18, 2020‏
1122020
The cat and mouse in split manufacturing‏
Y Wang, P Chen, J Hu, J Rajendran‏
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016‏
1102016
Fast algorithms for slew constrained minimum cost buffering‏
S Hu, CJ Alpert, J Hu, S Karandikar, Z Li, W Shi, CN Sze‏
Proceedings of the 43rd annual Design Automation Conference, 308-313, 2006‏
1042006
An efficient merging scheme for prescribed skew clock routing‏
R Chaturvedi, J Hu‏
IEEE transactions on very large scale integration (VLSI) systems 13 (6), 750-754, 2005‏
103*2005
Algorithms for gate sizing and device parameter selection for high-performance designs‏
MM Ozdal, S Burns, J Hu‏
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2012‏
99*2012
Gate sizing for cell library-based designs‏
S Hu, M Ketkar, J Hu‏
Proceedings of the 44th annual Design Automation Conference, 847-852, 2007‏
972007
Buffered Steiner trees for difficult instances‏
CJ Alpert, M Hrkić, J Hu, AB Kahng, J Lillis, B Liu, ST Quay, ...‏
Proceedings of the 2001 international symposium on Physical design, 4-9, 2001‏
932001
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מאמרים 1–20