| Colonnade: A reconfigurable SRAM-based digital bit-serial compute-in-memory macro for processing neural networks H Kim, T Yoo, TTH Kim, B Kim IEEE Journal of Solid-State Circuits 56 (7), 2221-2233, 2021 | 145 | 2021 |
| A 16K current-based 8T SRAM compute-in-memory macro with decoupled read/write and 1-5bit column ADC C Yu, T Yoo, TTH Kim, KCT Chuan, B Kim 2020 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2020 | 115 | 2020 |
| A 28nm 29.2 TFLOPS/W BF16 and 36.5 TOPS/W INT8 reconfigurable digital CIM processor with unified FP/INT pipeline and bitwise in-memory booth multiplication for cloud deep … F Tu, Y Wang, Z Wu, L Liang, Y Ding, B Kim, L Liu, S Wei, Y Xie, S Yin 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 100 | 2022 |
| True random number generator circuits based on single-and multi-phase beat frequency detection Q Tang, B Kim, Y Lao, KK Parhi, CH Kim Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014 | 93 | 2014 |
| A logic-compatible eDRAM compute-in-memory with embedded ADCs for processing neural networks C Yu, T Yoo, H Kim, TTH Kim, KCT Chuan, B Kim IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2), 667-679, 2020 | 77 | 2020 |
| A 65-nm 8T SRAM compute-in-memory macro with column ADCs for processing neural networks C Yu, T Yoo, KTC Chai, TTH Kim, B Kim IEEE Journal of Solid-State Circuits 57 (11), 3466-3476, 2022 | 75 | 2022 |
| A 1-16b precision reconfigurable digital in-memory computing macro featuring column-MAC architecture and bit-serial computation H Kim, Q Chen, T Yoo, TTH Kim, B Kim ESSCIRC 2019-IEEE 45th European Solid State Circuits Conference (ESSCIRC …, 2019 | 62 | 2019 |
| An overview of processing-in-memory circuits for artificial intelligence and machine learning D Kim, C Yu, S Xie, Y Chen, JY Kim, B Kim, JP Kulkarni, TTH Kim IEEE Journal on Emerging and Selected Topics in Circuits and Systems 12 (2 …, 2022 | 57 | 2022 |
| A 16K SRAM-based mixed-signal in-memory computing macro featuring voltage-mode accumulator and row-by-row ADC H Kim, Q Chen, B Kim 2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 35-36, 2019 | 44 | 2019 |
| Reconfigurable 2T2R ReRAM architecture for versatile data storage and computing in-memory Y Chen, L Lu, B Kim, TTH Kim IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (12 …, 2020 | 41 | 2020 |
| 31.2 CIM-spin: A 0.5-to-1.2 V scalable annealing processor using digital compute-in-memory spin operators and register-based spins for combinatorial optimization problems Y Su, H Kim, B Kim 2020 IEEE International Solid-State Circuits Conference-(ISSCC), 480-482, 2020 | 38 | 2020 |
| ReDCIM: Reconfigurable digital computing-in-memory processor with unified FP/INT pipeline for cloud AI acceleration F Tu, Y Wang, Z Wu, L Liang, Y Ding, B Kim, L Liu, S Wei, Y Xie, S Yin IEEE Journal of Solid-State Circuits 58 (1), 243-255, 2022 | 37 | 2022 |
| An 8bit, 2.6 ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier B Kim, H Kim, CH Kim 2015 IEEE Custom Integrated Circuits Conference (CICC), 1-4, 2015 | 37 | 2015 |
| A logic compatible 4T dual embedded DRAM array for in-memory computation of deep neural networks T Yoo, H Kim, Q Chen, TTH Kim, B Kim 2019 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2019 | 34 | 2019 |
| FlexSpin: A scalable CMOS Ising machine with 256 flexible spin processing elements for solving complex combinatorial optimization problems Y Su, TTH Kim, B Kim 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 31 | 2022 |
| SRAM-based in-memory computing macro featuring voltage-mode accumulator and row-by-row ADC for processing neural networks J Mu, H Kim, B Kim IEEE Transactions on Circuits and Systems I: Regular Papers 69 (6), 2412-2422, 2022 | 30 | 2022 |
| 4-level pulse amplitude modulation transmitter architectures utilizing quadrature clock phases TO Dickson, KIM Bongjin US Patent 9,674,025, 2017 | 30 | 2017 |
| 19.2 A 0.2-to-1.45 GHz subsampling fractional-N all-digital MDLL with zero-offset aperture PD-based spur cancellation and in-situ timing mismatch detection S Kundu, B Kim, CH Kim 2016 IEEE International Solid-State Circuits Conference (ISSCC), 326-327, 2016 | 30 | 2016 |
| A 1-16b reconfigurable 80Kb 7T SRAM-based digital near-memory computing macro for processing neural networks H Kim, J Mu, C Yu, TTH Kim, B Kim IEEE Transactions on Circuits and Systems I: Regular Papers 70 (4), 1580-1590, 2023 | 26 | 2023 |
| A scalable CMOS Ising computer featuring sparse and reconfigurable spin interconnects for solving combinatorial optimization problems Y Su, J Mu, H Kim, B Kim IEEE Journal of Solid-State Circuits 57 (3), 858-868, 2022 | 25 | 2022 |
Tony Tae-Hyoung KIMAssociate Professor, Nanyang Technological Universityכתובת אימייל מאומתת בדומיין ntu.edu.sg