עקוב אחר
Cheng-Wen Wu 吳誠文
Cheng-Wen Wu 吳誠文
Department of Electrical Engineering, National Tsing Hua University
כתובת אימייל מאומתת בדומיין ee.nthu.edu.tw - דף הבית
כותרת
צוטט על ידי
צוטט על ידי
שנה
VLSI test principles and architectures: design for testability‏
LT Wang, CW Wu, X Wen‏
Elsevier, 2006‏
9952006
RRAM defect modeling and failure analysis based on march test and a novel squeeze-search scheme‏
CY Chen, HC Shih, CW Wu, CH Lin, PF Chiu, SS Sheu, FT Chen‏
IEEE Transactions on Computers 64 (1), 180-190, 2014‏
2752014
Built-in redundancy analysis for memory yield improvement‏
CT Huang, CF Wu, JF Li, CW Wu‏
IEEE transactions on Reliability 52 (4), 386-399, 2003‏
2552003
On-chip TSV testing for 3D IC before bonding using sense amplification‏
PY Chen, CW Wu, DM Kwai‏
2009 Asian Test Symposium, 450-455, 2009‏
1812009
A programmable BIST core for embedded DRAM‏
CT Huang, JR Huang, CF Wu, CW Wu, TY Chang‏
IEEE Design & Test of Computers 16 (1), 59-70, 1999‏
1601999
On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding‏
PY Chen, CW Wu, DM Kwai‏
2010 28th VLSI Test Symposium (VTS), 263-268, 2010‏
1532010
A built-in self-repair design for RAMs with 2-D redundancy‏
JF Li, JC Yeh, RF Huang, CW Wu‏
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (6), 742-745, 2005‏
1352005
A high-throughput low-cost AES processor‏
CP Su, TF Lin, CT Huang, CW Wu‏
IEEE Communications Magazine 41 (12), 86-91, 2003‏
1342003
Efficient built-in redundancy analysis for embedded memories with 2-D redundancy‏
SK Lu, YC Tsai, CH Hsu, KH Wang, CW Wu‏
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (1), 34-42, 2006‏
1312006
Single-and multi-core configurable AES architectures for flexible security‏
MY Wang, CP Su, CL Horng, CW Wu, CT Huang‏
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (4), 541-552, 2009‏
1112009
IEEE Std. 1149.1 boundary scan circuit capable of built-in self-testing‏
CH Tsai, FD Guo, JH Hong, CW Wu‏
US Patent 5,570,375, 1996‏
1111996
RAMSES: a fast memory fault simulator‏
CF Wu, CT Huang, CW Wu‏
Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance …, 1999‏
1081999
An adaptive-rate error correction scheme for NAND flash memory‏
TH Chen, YY Hsiao, YT Hsing, CW Wu‏
2009 27th IEEE VLSI Test Symposium, 53-58, 2009‏
992009
An integrated ECC and redundancy repair scheme for memory reliability enhancement‏
CL Su, YT Yeh, CW Wu‏
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005‏
972005
March-based RAM diagnosis algorithms for stuck-at and coupling faults‏
JF Li, KL Cheng, CT Huang, CW Wu‏
Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 758-767, 2001‏
952001
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs‏
YJ Huang, JF Li, JJ Chen, DM Kwai, YF Chou, CW Wu‏
29th VLSI test symposium, 20-25, 2011‏
922011
A built-in self-repair scheme for semiconductor memories with 2-D redundancy‏
JF Li, JC Yeh, RF Huang, CW Wu, PY Tsai, A Hsu, E Chow‏
International Test Conference, 2003. Proceedings. ITC 2003., 393-393, 2003‏
922003
RSA cryptosystem design based on the Chinese remainder theorem‏
CH Wu, JH Hong, CW Wu‏
Proceedings of the 2001 Asia and South Pacific Design automation conference …, 2001‏
912001
Sequential circuit fault simulation using logic emulation‏
SA Hwang, JH Hong, CW Wu‏
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998‏
911998
Performance characterization of TSV in 3D IC via sensitivity analysis‏
JW You, SY Huang, DM Kwai, YF Chou, CW Wu‏
2010 19th IEEE Asian Test Symposium, 389-394, 2010‏
842010
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