| QNoC: QoS architecture and design process for network on chip E Bolotin, I Cidon, R Ginosar, A Kolodny Journal of systems architecture 50 (2-3), 105-128, 2004 | 811 | 2004 |
| MCM-GPU: Multi-chip-module GPUs for continued performance scalability A Arunkumar, E Bolotin, B Cho, U Milic, E Ebrahimi, O Villa, A Jaleel, ... ACM SIGARCH Computer Architecture News 45 (2), 320-332, 2017 | 264 | 2017 |
| Scaling the power wall: a path to exascale O Villa, DR Johnson, M Oconnor, E Bolotin, D Nellans, J Luitjens, ... SC'14: Proceedings of the International Conference for High Performance …, 2014 | 190 | 2014 |
| Many-core vs. many-thread machines: Stay away from the valley Z Guz, E Bolotin, I Keidar, A Kolodny, A Mendelson, UC Weiser IEEE Computer Architecture Letters 8 (1), 25-28, 2009 | 144 | 2009 |
| Cost considerations in network on chip E Bolotin, I Cidon, R Ginosar, A Kolodny Integration 38 (1), 19-42, 2004 | 140 | 2004 |
| Anatomy of gpu memory system for multi-application execution A Jog, O Kayiran, T Kesten, A Pattnaik, E Bolotin, N Chatterjee, ... Proceedings of the 2015 international symposium on memory systems, 223-234, 2015 | 119 | 2015 |
| The power of priority: NoC based distributed cache coherency E Bolotin, Z Guz, I Cidon, R Ginosar, A Kolodny First International Symposium on Networks-on-Chip (NOCS'07), 117-126, 2007 | 103 | 2007 |
| Beyond the socket: NUMA-aware GPUs U Milic, O Villa, E Bolotin, A Arunkumar, E Ebrahimi, A Jaleel, A Ramirez, ... Proceedings of the 50th Annual IEEE/ACM International Symposium on …, 2017 | 99 | 2017 |
| Routing table minimization for irregular mesh NoCs E Bolotin, I Cidon, R Ginosar, A Kolodny 2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007 | 99 | 2007 |
| A case for toggle-aware compression for GPU systems G Pekhimenko, E Bolotin, N Vijaykumar, O Mutlu, TC Mowry, SW Keckler 2016 IEEE International Symposium on High Performance Computer Architecture …, 2016 | 96 | 2016 |
| Combining HW/SW mechanisms to improve NUMA performance of multi-GPU systems V Young, A Jaleel, E Bolotin, E Ebrahimi, D Nellans, O Villa 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture …, 2018 | 95 | 2018 |
| Efficient link capacity and QoS design for network-on-chip Z Guz, I Walter, E Bolotin, I Cidon, R Ginosar, A Kolodny Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006 | 91 | 2006 |
| Application-aware memory system for fair and efficient execution of concurrent gpgpu applications A Jog, E Bolotin, Z Guz, M Parker, SW Keckler, MT Kandemir, CR Das Proceedings of workshop on general purpose processing using GPUs, 1-8, 2014 | 85 | 2014 |
| Network Delays and Link Capacities in Application‐Specific Wormhole NoCs Z Guz, I Walter, E Bolotin, I Cidon, R Ginosar, A Kolodny VLSI design 2007 (1), 090941, 2007 | 72 | 2007 |
| Automatic hardware-efficient SoC integration by QoS network on chip E Bolotin, A Morgenshtein, I Cidon, R Ginosar, A Kolodny Proceedings of the 2004 11th IEEE International Conference on Electronics …, 2004 | 62 | 2004 |
| Understanding the future of energy efficiency in multi-module gpus A Arunkumar, E Bolotin, D Nellans, CJ Wu 2019 IEEE International Symposium on High Performance Computer Architecture …, 2019 | 52 | 2019 |
| Need for speed: Experiences building a trustworthy system-level gpu simulator O Villa, D Lustig, Z Yan, E Bolotin, Y Fu, N Chatterjee, N Jiang, D Nellans 2021 IEEE International Symposium on High-Performance Computer Architecture …, 2021 | 47 | 2021 |
| Hmg: Extending cache coherence protocols across modern hierarchical multi-gpu systems X Ren, D Lustig, E Bolotin, A Jaleel, O Villa, D Nellans 2020 IEEE International Symposium on High Performance Computer Architecture …, 2020 | 44 | 2020 |
| Hybrid exclusive multi-level memory architecture with memory management DG Feekes, S Raikin, B Fanning, J Ray, J Mandelblat, A Berkovits, ... US Patent 9,734,079, 2017 | 39 | 2017 |
| Toggle-aware compression for GPUs G Pekhimenko, E Bolotin, M O’Connor, O Mutlu, TC Mowry, SW Keckler IEEE Computer Architecture Letters 14 (2), 164-168, 2015 | 31 | 2015 |
Avinoam KolodnyProfessor of Electrical and Computer Engineering, Technionכתובת אימייל מאומתת בדומיין ee.technion.ac.il