| Three-dimensional integrated circuits AW Topol, DC La Tulipe, L Shi, DJ Frank, K Bernstein, SE Steen, A Kumar, ... IBM Journal of Research and Development 50 (4.5), 491-506, 2006 | 916 | 2006 |
| Stable SRAM cell design for the 32 nm node and beyond L Chang, DM Fried, J Hergenrother, JW Sleight, RH Dennard, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 128-129, 2005 | 869 | 2005 |
| Three-dimensional silicon integration JU Knickerbocker, PS Andry, B Dang, RR Horton, MJ Interrante, CS Patel, ... IBM Journal of Research and Development 52 (6), 553-569, 2008 | 566 | 2008 |
| High density chip carrier with integrated passive devices MP Chudzik, RH Dennard, R Divakaruni, BK Furman, R Jammy, ... US Patent 7,030,481, 2006 | 376 | 2006 |
| Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs) AW Topol, DC La Tulipe, L Shi, SM Alam, DJ Frank, SE Steen, J Vichiconti, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 370 | 2005 |
| Layer transfer process and functionally enhanced integrated circuits produced thereby BK Furman, S Purushothaman, M Sankarapandian, A Topol US Patent 7,855,101, 2010 | 341 | 2010 |
| High density chip carrier with integrated passive devices MP Chudzik, RH Dennard, R Divakaruni, BK Furman, R Jammy, ... US Patent 6,962,872, 2005 | 333 | 2005 |
| Layer Transfer Process and Functionally Enhanced Integrated Circuits Products Thereby BK Furman, S Purushothaman, M Sankarapandian, A Topol US Patent App. 11/746,680, 2008 | 280 | 2008 |
| Methods of forming wiring to transistor and related transistor DJ Frank, DC La Tulipe Jr, SE Steen, AW Topol US Patent 7,666,723, 2010 | 274 | 2010 |
| Techniques for Layer Transfer Processing S Bedell, K Fogel, B Furman, S Purushothaman, D Sadana, A Topol US Patent App. 11/840,389, 2007 | 273 | 2007 |
| Overlay as the key to drive wafer scale 3D integration SE Steen, D LaTulipe, AW Topol, DJ Frank, K Belote, D Posillico Microelectronic engineering 84 (5-8), 1412-1415, 2007 | 269 | 2007 |
| Techniques for layer transfer processing S Bedell, K Fogel, B Furman, S Purushothaman, D Sadana, A Topol US Patent App. 10/685,636, 2005 | 249 | 2005 |
| Electrical integrity of state-of-the-art 0.13/spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication KW Guarini, AW Topol, M Ieong, R Yu, L Shi, MR Newport, DJ Frank, ... Digest. International Electron Devices Meeting,, 943-945, 2002 | 206 | 2002 |
| Servo control circuit for detecting analytes via nanoparticle-labeled substances with electromagnetic read-write heads TL Awezec, DJ Boday, SL Schwartz, AW Topol, DJ Winarski US Patent 8,694,280, 2014 | 106 | 2014 |
| Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures AW Topol, BK Furman, KW Guarini, L Shi, GM Cohen, GF Walker 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE …, 2004 | 96 | 2004 |
| Structure, design and process control for Cu bonded interconnects in 3D integrated circuits KN Chen, SH Lee, PS Andry, CK Tsang, AW Topol, YM Lin, JQ Lu, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 90 | 2006 |
| Transistor scaling with novel materials M Ieong, V Narayanan, D Singh, A Topol, V Chan, Z Ren Materials today 9 (6), 26-31, 2006 | 77 | 2006 |
| Highly scalable and distributed data sharing and storage S Oehme, MT Roskow, SL Schwartz, AW Topol, DJ Winarski US Patent 8,935,431, 2015 | 48 | 2015 |
| Structure and method of forming electrodeposited contacts C Cabral Jr, H Deligianni, RF Knarr, SG Malhotra, S Rossnagel, X Shao, ... US Patent 7,405,154, 2008 | 33 | 2008 |
| Hermetic seal and reliable bonding structures for 3d applications KN Chen, BK Furman, EJ Sprogis, AW Topol, CK Tsang, MR Wordeman, ... US Patent App. 11/534,366, 2008 | 33 | 2008 |