| Method for two-stage query optimization in massively parallel processing database clusters JY Sun, Q Zhou, M Singamshetty US Patent 9,311,354, 2016 | 219 | 2016 |
| Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder Y Sun, JR Cavallaro Integration 44 (4), 305-315, 2011 | 157 | 2011 |
| WARP, a unified wireless network testbed for education and research K Amiri, Y Sun, P Murphy, C Hunter, JR Cavallaro, A Sabharwal 2007 IEEE International Conference on Microelectronic Systems Education (MSE …, 2007 | 138 | 2007 |
| VLSI decoder architecture for high throughput, variable block-size and multi-rate LDPC codes Y Sun, M Karkooti, JR Cavallaro 2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2104-2107, 2007 | 106 | 2007 |
| High throughput, parallel, scalable LDPC encoder/decoder architecture for OFDM systems Y Sun, M Karkooti, JR Cavallaro 2006 IEEE Dallas/CAS workshop on design, applications, integration and …, 2006 | 89 | 2006 |
| Data placement control for distributed computing environment JY Sun, G Zhang, L Cai US Patent 10,055,458, 2018 | 86 | 2018 |
| Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards Y Sun, Y Zhu, M Goel, JR Cavallaro 2008 International Conference on Application-Specific Systems, Architectures …, 2008 | 77 | 2008 |
| A massively parallel implementation of QC-LDPC decoder on GPU G Wang, M Wu, Y Sun, JR Cavallaro 2011 IEEE 9th Symposium on Application Specific Processors (SASP), 82-85, 2011 | 74 | 2011 |
| A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards Y Sun, JR Cavallaro 2008 IEEE international SOC conference, 367-370, 2008 | 70 | 2008 |
| Implementation of a high throughput soft MIMO detector on GPU M Wu, Y Sun, S Gupta, JR Cavallaro Journal of Signal Processing Systems 64, 123-136, 2011 | 65 | 2011 |
| Dynamic computation node grouping with cost based optimization for massively parallel processing L Zhang, JY Sun, Y Ding US Patent 10,649,996, 2020 | 58 | 2020 |
| Parallel interleaver design for a high throughput HSPA+/LTE multi-standard turbo decoder G Wang, H Shen, Y Sun, JR Cavallaro, A Vosoughi, Y Guo IEEE Transactions on Circuits and Systems I: Regular Papers 61 (5), 1376-1389, 2014 | 54 | 2014 |
| Multi-layer parallel decoding algorithm and VLSI architecture for quasi-cyclic LDPC codes Y Sun, G Wang, JR Cavallaro 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 1776-1779, 2011 | 52 | 2011 |
| VLSI architecture for layered decoding of QC-LDPC codes with high circulant weight Y Sun, JR Cavallaro IEEE transactions on very large scale integration (VLSI) systems 21 (10 …, 2012 | 48 | 2012 |
| A flexible LDPC/turbo decoder architecture Y Sun, JR Cavallaro Journal of Signal Processing Systems 64, 1-16, 2011 | 48 | 2011 |
| Implementation of a high throughput 3GPP turbo decoder on GPU M Wu, Y Sun, G Wang, JR Cavallaro Journal of Signal Processing Systems 65, 171-183, 2011 | 47 | 2011 |
| Big data statistics at data-block level D Ni, G Zhang, Q Zhou, JY Sun US Patent App. 14/687,568, 2016 | 45 | 2016 |
| Implementation of a 3GPP LTE turbo decoder accelerator on GPU M Wu, Y Sun, JR Cavallaro 2010 IEEE Workshop On Signal Processing Systems, 192-197, 2010 | 38 | 2010 |
| Architectures for cognitive radio testbeds and demonstrators—an overview O Gustafsson, K Amiri, D Andersson, A Blad, C Bonnet, JR Cavallaro, ... 2010 Proceedings of the Fifth International Conference on Cognitive Radio …, 2010 | 38 | 2010 |
| A GPU implementation of a real-time MIMO detector M Wu, S Gupta, Y Sun, JR Cavallaro 2009 IEEE Workshop on Signal Processing Systems, 303-308, 2009 | 36 | 2009 |
Joseph R. CavallaroProfessor of Electrical and Computer Engineering, Rice UniversityEmail verificata su rice.edu
