| Dreamplace: Deep learning toolkit-enabled gpu acceleration for modern vlsi placement Y Lin, S Dhar, W Li, H Ren, B Khailany, DZ Pan Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 261 | 2019 |
| RouteNet: Routability prediction for mixed-size designs using convolutional neural network Z Xie, YH Huang, GQ Fang, H Ren, SY Fang, Y Chen, J Hu 2018 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 1-8, 2018 | 197 | 2018 |
| High performance graph convolutional networks with applications in testability analysis Y Ma, H Ren, B Khailany, H Sikka, L Luo, K Natarajan, B Yu Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 133 | 2019 |
| GRANNITE: Graph neural network inference for transferable power estimation Y Zhang, H Ren, B Khailany 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 106 | 2020 |
| Chipnemo: Domain-adapted llms for chip design M Liu, TD Ene, R Kirby, C Cheng, N Pinckney, R Liang, J Alben, H Anand, ... arXiv preprint arXiv:2311.00176, 2023 | 101 | 2023 |
| Sensitivity guided net weighting for placement driven synthesis TY Wang, JL Tsai, CCP Chen Proceedings of the 2004 international symposium on Physical design, 124-131, 2004 | 101 | 2004 |
| PowerNet: Transferable dynamic IR drop estimation via maximum convolutional neural network Z Xie, H Ren, B Khailany, Y Sheng, S Santosh, J Hu, Y Chen 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC), 13-18, 2020 | 97 | 2020 |
| Verilogeval: Evaluating large language models for verilog code generation M Liu, N Pinckney, B Khailany, H Ren 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-8, 2023 | 95 | 2023 |
| ParaGraph: Layout parasitics and device parameter prediction using graph neural networks H Ren, GF Kokai, WJ Turner, TS Ku 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 94 | 2020 |
| RQL: Global placement via relaxed quadratic spreading and linearization N Viswanathan, GJ Nam, CJ Alpert, P Villarrubia, H Ren, C Chu Proceedings of the 44th annual Design Automation Conference, 453-458, 2007 | 92 | 2007 |
| Techniques for fast physical synthesis CJ Alpert, SK Karandikar, Z Li, GJ Nam, ST Quay, H Ren, CN Sze, ... Proceedings of the IEEE 95 (3), 573-599, 2007 | 86 | 2007 |
| PRIMAL: Power inference using machine learning Y Zhou, H Ren, Y Zhang, B Keller, B Khailany, Z Zhang Proceedings of the 56th Annual Design Automation Conference 2019, 1-6, 2019 | 84 | 2019 |
| Accelerating chip design with machine learning B Khailany Proceedings of the 2020 ACM/IEEE Workshop on Machine Learning for CAD, 33-33, 2020 | 83 | 2020 |
| Relative ordering circuit synthesis M Cho, R Puri, H Ren, X Tang, H Xiang, MM Ziegler US Patent 8,756,541, 2014 | 83 | 2014 |
| Diffusion-based placement migration H Ren, DZ Pan, CJ Alpert, P Villarrubia Proceedings of the 42nd annual Design Automation Conference, 515-520, 2005 | 82 | 2005 |
| DeltaSyn: An efficient logic difference optimizer for ECO synthesis S Krishnaswamy, H Ren, N Modi, R Puri Proceedings of the 2009 International Conference on Computer-Aided Design …, 2009 | 72 | 2009 |
| Vs-quant: Per-vector scaled quantization for accurate low-precision neural network inference S Dai, R Venkatesan, H Ren, B Zimmer, WJ Dally, B Khailany arXiv preprint arXiv:2102.04503, 2021 | 56 | 2021 |
| Routability-driven macro placement with embedded cnn-based prediction model YH Huang, Z Xie, GQ Fang, TC Yu, H Ren, SY Fang, Y Chen, J Hu 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE), 180-185, 2019 | 55 | 2019 |
| Abcdplace: Accelerated batch-based concurrent detailed placement on multithreaded cpus and gpus Y Lin, W Li, J Gu, H Ren, B Khailany, DZ Pan IEEE transactions on computer-aided design of integrated circuits and …, 2020 | 54 | 2020 |
| Converged large block and structured synthesis for high performance microprocessor designs M Cho, VN Kravets, S Krishnaswamy, D Kucar, J Narasimhan, R Puri, ... US Patent 8,271,920, 2012 | 52 | 2012 |