| A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging K Mistry, C Allen, C Auth, B Beattie, D Bergstrom, M Bost, M Brazier, ... 2007 IEEE International Electron Devices Meeting, 247-250, 2007 | 1689 | 2007 |
| A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors T Ghani, M Armstrong, C Auth, M Bost, P Charvat, G Glass, T Hoffmann, ... IEEE International Electron Devices Meeting 2003, 11.6. 1-11.6. 3, 2003 | 1073 | 2003 |
| A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors C Auth, C Allen, A Blattner, D Bergstrom, M Brazier, M Bost, M Buehler, ... 2012 symposium on VLSI technology (VLSIT), 131-132, 2012 | 1038 | 2012 |
| A 90-nm logic technology featuring strained-silicon SE Thompson, M Armstrong, C Auth, M Alavi, M Buehler, R Chau, S Cea, ... IEEE Transactions on electron devices 51 (11), 1790-1797, 2004 | 942 | 2004 |
| A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size S Natarajan, M Agostinelli, S Akbar, M Bost, A Bowonder, V Chikarmane, ... 2014 IEEE international electron devices meeting, 3.7. 1-3.7. 3, 2014 | 764 | 2014 |
| A logic nanotechnology featuring strained-silicon SE Thompson, M Armstrong, C Auth, S Cea, R Chau, G Glass, T Hoffman, ... IEEE Electron Device Letters 25 (4), 191-193, 2004 | 694 | 2004 |
| 45nm high-k+ metal gate strain-enhanced transistors C Auth, A Cappellani, JS Chun, A Dalis, A Davis, T Ghani, G Glass, ... 2008 Symposium on VLSI Technology, 128-129, 2008 | 603 | 2008 |
| Semiconductor transistor having a stressed channel A Murthy, RS Chau, T Ghani, KR Mistry US Patent 6,621,131, 2003 | 536 | 2003 |
| The high-k solution MT Bohr, RS Chau, T Ghani, K Mistry IEEE spectrum 44 (10), 29-35, 2007 | 524 | 2007 |
| III-V layers for N-type and P-type MOS source-drain contacts GA Glass, AS Murthy, T Ghani US Patent 9,153,583, 2015 | 507 | 2015 |
| A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1/spl mu/m/sup 2/SRAM cell S Thompson, N Anand, M Armstrong, C Auth, B Arcot, M Alavi, P Bai, ... Digest. International Electron Devices Meeting,, 61-64, 2002 | 455 | 2002 |
| Non-planar semiconductor device having doped sub-fin region and method to fabricate same T Ghani, S Latif, CD Munasinghe US Patent 10,056,380, 2018 | 396 | 2018 |
| Self-aligned contacts MT Bohr, T Ghani, NM Rahhal-Orabi, SM Joshi, JM Steigerwald, JW Klaus, ... US Patent 8,436,404, 2013 | 310 | 2013 |
| High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors P Packan, S Akbar, M Armstrong, D Bergstrom, M Brazier, H Deshpande, ... 2009 IEEE international electron devices meeting (IEDM), 1-4, 2009 | 291 | 2009 |
| A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2SRAM cell size in a 291Mb array S Natarajan, M Armstrong, M Bost, R Brain, M Brazier, CH Chang, ... 2008 IEEE International Electron Devices Meeting, 1-3, 2008 | 286 | 2008 |
| Semiconductor device having doped epitaxial region and its methods of fabrication AS Murtthy, DB Aubertine, T Ghani, AJ Pethe US Patent 8,598,003, 2013 | 273 | 2013 |
| Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors T Ghani, K Mistry, P Packan, S Thompson, M Stettler, S Tyagi, M Bohr 2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2000 | 273 | 2000 |
| In search of" forever," continued transistor scaling one new material at a time SE Thompson, RS Chau, T Ghani, K Mistry, S Tyagi, MT Bohr IEEE Transactions on semiconductor manufacturing 18 (1), 26-36, 2005 | 266 | 2005 |
| Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs A Keshavarzi, S Ma, S Narendra, B Bloechel, K Mistry, T Ghani, S Borkar, ... Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 255 | 2001 |
| PMOS transistor strain optimization with raised junction regions M Bohr, T Ghani, S Cea, K Mistry, C Auth, M Armstrong, K Zawadzki US Patent App. 10/608,870, 2004 | 231 | 2004 |
