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Bashar Romanous
Bashar Romanous
Senior Systems Design/Architect Engineer at Micron Technology
Email verificata su micron.com - Home page
Titolo
Citata da
Citata da
Anno
Network densification: Challenges and opportunities in enabling 5G
B Romanous, N Bitar, A Imran, H Refai
2015 IEEE 20th international workshop on computer aided modelling and design …, 2015
882015
A game theoretic approach for optimizing density of remote radio heads in user centric cloud-based radio access network
B Romanous, N Bitar, SAR Zaidi, A Imran, M Ghogho, HH Refai
2015 IEEE Global Communications Conference (GLOBECOM), 1-6, 2015
152015
An operating system for a reconfigurable active SSD processing node
A Ali, M Jomaa, B Romanous, M Sharafeddine, MAR Saghir, H Akkary, ...
2012 19th International Conference on Telecommunications (ICT), 1-6, 2012
112012
Reinforcement learning approach for mapping applications to dataflow-based coarse-grained reconfigurable array
AXM Chang, P Khopkar, B Romanous, A Chaurasia, P Estep, S Windh, ...
arXiv preprint arXiv:2205.13675, 2022
72022
High-performance parallel radix sort on fpga
B Romanous, M Rezvani, J Huang, D Wong, EE Papalexakis, VJ Tsotras, ...
2020 IEEE 28th Annual International Symposium on Field-Programmable Custom …, 2020
72020
A mediation layer for connecting data-intensive applications to reconfigurable data nodes
M Jomaa, K Mershad, N Abbani, Y Sharaf-Dabbagh, B Romanous, ...
2013 22nd International Conference on Computer Communication and Networks …, 2013
62013
Efficient local locking for massively multithreaded in-memory hash-based operators
B Romanous, S Windh, I Absalyamov, P Budhkar, R Halstead, W Najjar, ...
The VLDB Journal 30 (3), 333-359, 2021
32021
Programming a coarse grained reconfigurable array through description of data flow graphs
SA Windh, AK Porterfield, DJ Vanesko, RP Meyer, PA Estep, B Romanous
US Patent 11,815,935, 2023
12023
Schedule Instructions of a Program of Data Flows for Execution in Tiles of a Coarse Grained Reconfigurable Array
AK Porterfield, SA Windh, B Romanous
US Patent App. 18/770,560, 2024
2024
Design Space Exploration for Mapping Workloads to Circuit Units in a Computing Device
B Romanous, PA Estep, SA Windh
US Patent App. 18/590,449, 2024
2024
Schedule instructions of a program of data flows for execution in tiles of a coarse grained reconfigurable array
AK Porterfield, SA Windh, B Romanous
US Patent 12,039,335, 2024
2024
Mapping Workloads to Circuit Units in a Computing Device via Reinforcement Learning
AXM Chang, A Chaurasia, P Khopkar, B Romanous, PA Estep, SA Windh, ...
US Patent App. 18/185,031, 2023
2023
On the Acceleration of Database Primitives on FPGAs
B Romanous
University of California, Riverside, 2021
2021
Development and integration of RASSD node operating system and SATA Interface
BF Romanous
Theses, Dissertations, and Projects, 2013
2013
Il sistema al momento non può eseguire l'operazione. Riprova più tardi.
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