| Parameter variations and impact on circuits and microarchitecture S Borkar, T Karnik, S Narendra, J Tschanz, A Keshavarzi, V De Proceedings of the 40th annual Design Automation Conference, 338-342, 2003 | 1913 | 2003 |
| Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage JW Tschanz, JT Kao, SG Narendra, R Nair, DA Antoniadis, ... IEEE Journal of Solid-State Circuits 37 (11), 1396-1402, 2002 | 1001 | 2002 |
| A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS J Howard, S Dighe, Y Hoskote, S Vangal, D Finan, G Ruhl, D Jenkins, ... 2010 IEEE International Solid-State Circuits Conference-(ISSCC), 108-109, 2010 | 859 | 2010 |
| A 48-core IA-32 processor in 45 nm CMOS using on-die message-passing and DVFS for performance and power scaling J Howard, S Dighe, SR Vangal, G Ruhl, N Borkar, S Jain, V Erraguntla, ... IEEE Journal of Solid-State Circuits 46 (1), 173-183, 2010 | 527 | 2010 |
| Technology and design challenges for low power and high performance V De, S Borkar Proceedings of the 1999 international symposium on Low power electronics and …, 1999 | 510 | 1999 |
| A stochastic wire-length distribution for gigascale integration (GSI). I. Derivation and validation JA Davis, VK De, JD Meindl IEEE Transactions on Electron Devices 45 (3), 580-589, 1998 | 508* | 1998 |
| Scaling of stack effect and its application for leakage reduction S Narendra, V De, D Antoniadis, A Chandrakasan, S Borkar Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 476 | 2001 |
| Energy-efficient and metastability-immune resilient circuits for dynamic variation tolerance KA Bowman, JW Tschanz, NS Kim, JC Lee, CB Wilkerson, SLL Lu, ... IEEE Journal of Solid-State Circuits 44 (1), 49-63, 2008 | 455 | 2008 |
| A new technique for standby leakage reduction in high-performance circuits Y Ye, S Borkar, V De 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No …, 1998 | 440 | 1998 |
| Design and optimization of dual-threshold circuits for low-voltage low-power applications L Wei, Z Chen, K Roy, MC Johnson, Y Ye, VK De IEEE Transactions on Very Large Scale Integration (VLSI) Systems 7 (1), 16-24, 1999 | 415 | 1999 |
| A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package P Hazucha, G Schrom, J Hahn, BA Bloechel, P Hack, GE Dermer, ... IEEE Journal of Solid-State Circuits 40 (4), 838-845, 2005 | 414 | 2005 |
| Dynamic sleep transistor and body bias for active leakage power control of microprocessors JW Tschanz, SG Narendra, Y Ye, BA Bloechel, S Borkar, V De IEEE Journal of Solid-State Circuits 38 (11), 1838-1845, 2003 | 398 | 2003 |
| Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors J Tschanz, S Narendra, Z Chen, S Borkar, M Sachdev, V De Proceedings of the 2001 international symposium on Low power electronics and …, 2001 | 349 | 2001 |
| A 280mV-to-1.2 V wide-operating-range IA-32 processor in 32nm CMOS S Jain, S Khare, S Yada, V Ambili, P Salihundam, S Ramani, ... 2012 IEEE international solid-state circuits conference, 66-68, 2012 | 347 | 2012 |
| Intrinsic MOSFET parameter fluctuations due to random dopant placement X Tang, VK De, JD Meindl IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5 (4), 369-376, 1997 | 341 | 1997 |
| A 45 nm resilient microprocessor core for dynamic variation tolerance KA Bowman, JW Tschanz, SLL Lu, PA Aseron, MM Khellah, ... IEEE Journal of Solid-State Circuits 46 (1), 194-208, 2010 | 337 | 2010 |
| Floating-body dynamic random access memory and method of fabrication in tri-gate technology SH Tang, A Keshavarzi, D Somasekhar, F Paillet, MM Khellah, Y Ye, ... US Patent 7,098,507, 2006 | 328 | 2006 |
| Design and optimization of low voltage high performance dual threshold CMOS circuits L Wei, Z Chen, M Johnson, K Roy, V De Proceedings of the 35th annual Design Automation Conference, 489-494, 1998 | 308 | 1998 |
| Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging J Tschanz, NS Kim, S Dighe, J Howard, G Ruhl, S Vangal, S Narendra, ... 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 276 | 2007 |
| 16.2 A 0.19 pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS SK Mathew, SK Satpathy, MA Anders, H Kaul, SK Hsu, A Agarwal, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 266 | 2014 |