A 2D analytical cylindrical gate tunnel FET (CG-TFET) model: impact of shortest tunneling distance S Dash, GP Mishra
Advances in Natural Sciences: Nanoscience and Nanotechnology 6 (3), 035005, 2015
64 2015 A new analytical threshold voltage model of cylindrical gate tunnel FET (CG-TFET) S Dash, GP Mishra
Superlattices and Microstructures 86, 211-220, 2015
57 2015 Performance analysis of undoped cylindrical gate all around (GAA) MOSFET at subthreshold regime B Jena, KP Pradhan, S Dash, GP Mishra, PK Sahu, SK Mohapatra
Advances in Natural Sciences: Nanoscience and Nanotechnology 6 (3), 035010, 2015
54 2015 Investigation on cylindrical gate all around (GAA) to nanowire MOSFET for circuit application B Jena, KP Pradhan, PK Sahu, S Dash, GP Mishra, SK Mohapatra
Facta universitatis-series: Electronics and Energetics 28 (4), 637-643, 2015
41 2015 Improved switching speed of a CMOS inverter using work-function modulation engineering B Jena, S Dash, GP Mishra
IEEE transactions on electron devices 65 (6), 2422-2429, 2018
37 2018 Inner-gate-engineered GAA MOSFET to enhance the electrostatic integrity B Jena, S Dash, SR Routray, GP Mishra
Nano 14 (10), 1950128, 2019
31 2019 A new analytical drain current model of cylindrical gate silicon tunnel FET with source δ-doping S Dash, B Jena, GP Mishra
Superlattices and Microstructures 97, 231-241, 2016
29 2016 Improved cut-off frequency for cylindrical gate TFET using source delta doping S Dash, GS Sahoo, GP Mishra
Procedia Technology 25, 450 – 455, 2016
27 2016 Impact of source-pocket engineering on device performance of dielectric modulated tunnel FET GD Das, GP Mishra, S Dash
Superlattices and Microstructures 124, 131-138, 2018
26 2018 Impact of technology scaling on analog and RF performance of SOI–TFET P Kumari, S Dash, GP Mishra
Advances in Natural Sciences: Nanoscience and Nanotechnology 6 (4), 045005, 2015
24 2015 Z‐shaped gate TFET with horizontal pocket for improvement of electrostatic behavior S Sahoo, S Dash, SR Routray, GP Mishra
International Journal of Numerical Modelling: Electronic Networks, Devices …, 2021
23 2021 Subthreshold swing minimization of cylindrical tunnel FET using binary metal alloy gate S Dash, GS Sahoo, GP Mishra
Superlattices and Microstructures 91, 105-111, 2016
23 2016 Conical surrounding gate MOSFET: a possibility in gate-all-around family B Jena, BS Ramkrishna, S Dash, GP Mishra
Advances in Natural Sciences: Nanoscience and Nanotechnology 7 (1), 015009, 2016
23 2016 Analysis of outliers in system identification using WLMS algorithm S Dash, MN Mohanty
2012 International Conference on Computing, Electronics and Electrical …, 2012
23 2012 Work-function modulated hetero gate charge plasma TFET to enhance the device performance S Sahoo, S Dash, GP Mishra
2019 Devices for Integrated Circuit (DevIC), 461-464, 2019
22 2019 Delta-doped tunnel FET (D-TFET) to improve current ratio ( S Panda, S Dash, SK Behera, GP Mishra
Journal of Computational Electronics 15, 857-864, 2016
22 2016 Electrostatic performance improvement of dual material cylindrical gate MOSFET using work-function modulation technique B Jena, S Dash, GP Mishra
Superlattices and microstructures 97, 212-220, 2016
22 2016 Impact of drain doping engineering on ambipolar and high-frequency performance of ZHP line-TFET S Sahoo, S Dash, SR Routray, GP Mishra
Semiconductor Science and Technology 35 (6), 065003, 2020
21 2020 An extensive electrostatic analysis of dual material gate all around tunnel FET (DMGAA-TFET) S Dash, GP Mishra
Advances in Natural Sciences: Nanoscience and Nanotechnology 7 (2), 025012, 2016
21 2016 Drain dielectric pocket engineering: its impact on the electrical performance of a hetero-structure tunnel FET S Panda, S Dash
Silicon 14 (15), 9305-9317, 2022
19 2022 
Guru Prasad Subas Chandra MishraProfessor, National Institute of Technology, RaipurEmail verificata su nitrr.ac.in
