Chih-Kong Ken Yang

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Mark HorowitzProfessor of Electrical Engineering and Computer ScienceEmail verificata su ee.stanford.edu
Amr Amin HafezAMS Architect at Apple Inc.Email verificata su ucla.edu
Ming-Shuan ChenSerDes Design Lead at Apple Inc.Email verificata su g.ucla.edu
Jintae KimProfessor in Electrical and Electronics Engineering, Konkuk UniversityEmail verificata su konkuk.ac.kr
Vladimir StojanovicProfessor of Electrical Engineering and Computer Sciences, University of CaliforniaEmail verificata su berkeley.edu
Sudhakar PamartiProfessor of Electrical and Computer Engineering, UCLAEmail verificata su ee.ucla.edu
Fengbo RenAssociate Professor, Arizona State UniversityEmail verificata su asu.edu
Dejan MarkovicProfessor of Electrical and Computer Engineering, UCLAEmail verificata su ee.ucla.edu
Tamer AliDirector of Analog and Circuit Technology at MediaTekEmail verificata su ee.ucla.edu
Alexander RylyakovNokiaEmail verificata su nokia.com
Ping-Hsuan HsiehAssistant Professor of Electrical Engineering, National Tsing Hua UniversityEmail verificata su ee.nthu.edu.tw
Richard DorranceResearch Scientist at Intel LabsEmail verificata su intel.com
Stefanos Sidiropoulos.Email verificata su alumni.stanford.edu
Lieven VandenbergheUCLAEmail verificata su ucla.edu
Bruce WooleyProfessor of Electrical Engineering, Emeritus; Stanford UniversityEmail verificata su ee.stanford.edu
Daniel FriedmanIBMEmail verificata su us.ibm.com
JCS WooUniversity of California, Los AngelesEmail verificata su ee.ucla.edu
William DallyChief Scientist, NVIDIA; Adjunct Professor of CS and EE, Stanford University;Email verificata su stanford.edu
Jack W. JudyNIMET, University of FloridaEmail verificata su ufl.edu
Jaeha KimElectrical and Computer Engineering, Seoul National University, KoreaEmail verificata su snu.ac.kr

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Chih-Kong Ken Yang

Professor of Electrical Engineering, UCLA

Email verificata su ee.ucla.edu


Titolo Ordina per citazioni Ordina per anno Ordina per titolo	Citata da Citata da	Anno
High-speed electrical signaling: Overview and limitations M Horowitz, CKK Yang, S Sidiropoulos IEEE Micro 18 (1), 12-24, 1998	303	1998
A 0.3-/spl mu/m CMOS 8-Gb/s 4-PAM serial link transceiver R Farjad-Rad, CKK Yang, MA Horowitz IEEE Journal of Solid-State Circuits 35 (5), 757-764, 2000	301	2000
Fast frequency acquisition phase-frequency detectors for GSa/s phase-locked loops M Mansuri, D Liu, CKK Yang Proceedings of the 27th European Solid-State Circuits Conference, 333-336, 2001	282	2001
A 0.5-/spl mu/m CMOS 4.0-Gbit/s serial link transceiver with data recovery using oversampling CKK Yang, R Farjad-Rad, MA Horowitz IEEE Journal of Solid-State Circuits 33 (5), 713-722, 1998	264	1998
A 0.4-/spl mu/m CMOS 10-Gb/s 4-PAM pre-emphasis serial link transmitter R Farjad-Rad, CKK Yang, MA Horowitz, TH Lee IEEE Journal of Solid-State Circuits 34 (5), 580-585, 1999	202	1999
A 27-mW 3.6-gb/s I/O transceiver KLJ Wong, H Hatamkhani, M Mansuri, CKK Yang IEEE Journal of Solid-State Circuits 39 (4), 602-612, 2004	200	2004
A 0.8-/spl mu/m CMOS 2.5 Gb/s oversampling receiver and transmitter for serial links CKK Yang, MA Horowitz IEEE Journal of Solid-State Circuits 31 (12), 2015-2023, 1996	182	1996
A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation M Mansuri, CKK Yang IEEE Journal of Solid-State Circuits 38 (11), 1804-1812, 2003	151	2003
Offset compensation in comparators with minimum input-referred supply noise KLJ Wong, CKK Yang IEEE Journal of Solid-State Circuits 39 (5), 837-840, 2004	141	2004
A serial-link transceiver based on 8-GSamples/s A/D and D/A converters in 0.25-/spl mu/m CMOS CKK Yang, V Stojanovic, S Modjtahedi, MA Horowitz, WF Ellersick IEEE Journal of Solid-State Circuits 36 (11), 1684-1692, 2001	119	2001
Design of high-speed serial links in CMOS CKK Yang Stanford University, 1999	113	1999
GAD: A 12-GS/s CMOS 4-bit A/D converter for an equalized multi-level link W Ellersick, CKK Yang, M Horowitz, W Dally 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No. 99CH36326 …, 1999	106	1999
A 6.0-mW 10.0-Gb/s receiver with switched-capacitor summation DFE A Emami-Neyestanak, A Varzaghani, JF Bulzacchelli, A Rylyakov, ... IEEE Journal of Solid-State Circuits 42 (4), 889-896, 2007	104	2007
Scalability and design-space analysis of a 1T-1MTJ memory cell for STT-RAMs R Dorrance, F Ren, Y Toriyama, AA Hafez, CKK Yang, D Markovic IEEE Transactions on Electron Devices 59 (4), 878-887, 2012	98	2012
A 5-mW 6-Gb/s quarter-rate sampling receiver with a 2-tap DFE using soft decisions KLJ Wong, A Rylyakov, CKK Yang IEEE Journal of Solid-State Circuits 42 (4), 881-888, 2007	91	2007
A CMOS 500 Mbps/pin synchronous point to point link interface S Sidiropoulos, CKK Yang, M Horowitz Proceedings of 1994 IEEE Symposium on VLSI Circuits, 43-44, 1994	85	1994
Power optimized ADC-based serial link receiver EH Chen, R Yousry, CKK Yang IEEE Journal of Solid-State Circuits 47 (4), 938-951, 2012	84	2012
Techniques for improving the accuracy of geometric-programming based analog circuit design optimization J Kim, J Lee, L Vandenberghe, CKK Yang IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004 …, 2004	82	2004
A 14-bit, 10-Msamples/s D/A converter using multibit/spl Sigma//spl Delta/modulation K Falakshahi, CKK Yang, BA Wooley IEEE Journal of Solid-State Circuits 34 (5), 607-615, 1999	72	1999
Delay-locked loops-an overview CKK Yang Phase-Locking in High-Performance Systems: From Devices to Architectures, 13-22, 2003	69	2003

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