| High-performance packet classification on GPU S Zhou, SG Singapura, VK Prasanna 2014 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2014 | 126 | 2014 |
| Recall: Reordered cache aware locality based graph processing K Lakhotia, S Singapura, R Kannan, V Prasanna 2017 IEEE 24th International Conference on High Performance Computing (HiPC …, 2017 | 38 | 2017 |
| Design and implementation of parallel pagerank on multicore platforms S Zhou, K Lakhotia, SG Singapura, H Zeng, R Kannan, VK Prasanna, ... 2017 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2017 | 29 | 2017 |
| Quickly finding a truss in a haystack O Green, J Fox, E Kim, F Busato, N Bombieri, K Lakhotia, S Zhou, ... 2017 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2017 | 29 | 2017 |
| Oscar: Optimizing scratchpad reuse for graph processing SG Singapura, A Srivastava, R Kannan, VK Prasanna 2017 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2017 | 14 | 2017 |
| Energy performance of fpgas on perfect suite kernels SR Kuppannagari, R Chen, A Sanny, SG Singapura, GPC Tran, S Zhou, ... 2014 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2014 | 14 | 2014 |
| FPGA based accelerator for pattern matching in YARA framework SG Singapura, YHE Yang, A Panangadan, T Nemeth, VK Prasanna Univ. Southern California, Los Angeles, CA, USA, Tech. Rep. CENG-2015–05, 2015 | 7 | 2015 |
| Fpga-based acceleration of pattern matching in yara SG Singapura, YHE Yang, A Panangadan, T Nemeth, P Ng, VK Prasanna International Symposium on Applied Reconfigurable Computing, 320-327, 2016 | 6 | 2016 |
| Optimal dynamic data layouts for 2D FFT on 3D memory integrated FPGA R Chen, SG Singapura, VK Prasanna The Journal of Supercomputing 73, 652-663, 2017 | 5 | 2017 |
| Performance modeling of matrix multiplication on 3D memory integrated FPGA SG Singapura, A Panangadan, VK Prasanna 2015 IEEE International Parallel and Distributed Processing Symposium …, 2015 | 4 | 2015 |
| Towards performance modeling of 3D memory integrated FPGA architectures SG Singapura, A Panangadan, VK Prasanna Applied Reconfigurable Computing: 11th International Symposium, ARC 2015 …, 2015 | 4 | 2015 |
| On-chip memory efficient data layout for 2D FFT on 3D memory integrated FPGA SG Singapura, R Kannan, VK Prasanna 2016 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2016 | 3 | 2016 |
| Area efficient reconfigurable architecture for current control loop of a servo controller SG Shreyas, L Vachhani 2012 IEEE 7th International Conference on Industrial and Information Systems …, 2012 | 2 | 2012 |
| Optimal data layout for block-level random accesses to scratchpad SG Singapura, R Kannan, VK Prasanna 2017 IEEE High Performance Extreme Computing Conference (HPEC), 1-7, 2017 | 1 | 2017 |
| Palchaudhuri, Ayan 104 Panda, Dhabaleswar K.(DK) 84, 213, 62 Panyala, Ajay 23 Park, Yoonho 94 V Pascucci, K Komatsu, K Kothapalli, S Krishnamoorthy, S Kumar, SE Kurt, ... | | |
Shijie ZhouUniversity of Southern CaliforniaEmail verificata su usc.edu
