| Performance evaluation and design trade-offs for network-on-chip interconnect architectures PP Pande, C Grecu, M Jones, A Ivanov, R Saleh IEEE transactions on Computers 54 (8), 1025-1040, 2005 | 1106 | 2005 |
| System-on-chip: Reuse and integration R Saleh, S Wilton, S Mirabbasi, A Hu, M Greenstreet, G Lemieux, ... Proceedings of the IEEE 94 (6), 1050-1069, 2006 | 405 | 2006 |
| Design of a switch for network on chip applications PP Pande, C Grecu, A Ivanov, R Saleh 2003 IEEE International Symposium on Circuits and Systems (ISCAS) 5, V-V, 2003 | 294 | 2003 |
| Design, synthesis, and test of networks on chips PP Pande, C Grecu, A Ivanov, R Saleh, G De Micheli IEEE Design & Test of Computers 22 (5), 404-413, 2005 | 248 | 2005 |
| Time monitoring appliance A Ivanov, AA Lowe US Patent 5,774,425, 1998 | 150 | 1998 |
| A small-window moving average-based fully automated baseline estimation method for Raman spectra HG Schulze, RB Foist, K Okuda, A Ivanov, RFB Turner Applied spectroscopy 66 (7), 757-764, 2012 | 129 | 2012 |
| Guest editors' introduction: The network-on-chip paradigm in practice and research A Ivanov, G De Micheli IEEE Design & Test of Computers 22 (5), 399-403, 2005 | 129 | 2005 |
| BIST for network-on-chip interconnect infrastructures C Grecu, P Pande, A Ivanov, R Saleh 24th IEEE VLSI Test Symposium, 6 pp.-35, 2006 | 128 | 2006 |
| Jitter models for the design and test of Gbps-speed serial interconnects N Ou, T Farahmand, A Kuo, S Tabatabaei, A Ivanov IEEE Design & Test of Computers 21 (4), 302-313, 2004 | 121 | 2004 |
| On-line fault detection and location for NoC interconnects C Grecu, A Ivanov, R Saleh, ES Sogomonyan, PP Pande 12th IEEE International On-Line Testing Symposium (IOLTS'06), 6 pp., 2006 | 111 | 2006 |
| Embedded timing analysis: A SoC infrastructure S Tabatabaei, A Ivanov IEEE Design & Test of Computers 19 (03), 24-36, 2002 | 107 | 2002 |
| Testing network-on-chip communication fabrics C Grecu, A Ivanov, R Saleh, PP Pande IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2007 | 100 | 2007 |
| High resolution time-to-digital converter S Tabatabaei, A Ivanov US Patent 6,754,613, 2004 | 85 | 2004 |
| Methodologies and algorithms for testing switch-based NoC interconnects C Grecu, P Pande, B Wang, A Ivanov, R Saleh 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005 | 83 | 2005 |
| High-throughput switch-based interconnect for future SoCs PP Pande, C Grecu, A Ivanov, R Saleh The 3rd IEEE International Workshop on System-on-Chip for Real-Time …, 2003 | 78 | 2003 |
| A 0.35/spl mu/m CMOS comparator circuit for high-speed ADC applications S Sheikhaei, S Mirabbasi, A Ivanov 2005 IEEE International Symposium on Circuits and Systems, 6134-6137, 2005 | 77 | 2005 |
| Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs C Grecu, PP Pande, A Ivanov, R Saleh Proceedings of the 14th ACM Great Lakes symposium on VLSI, 192-195, 2004 | 77 | 2004 |
| A scalable communication-centric SoC interconnect architecture C Grecu, PP Pande, A Ivanov, R Saleh International Symposium on Signals, Circuits and Systems. Proceedings, SCS …, 2004 | 74 | 2004 |
| Timing analysis of network on chip architectures for MP-SoC platforms C Grecu, PP Pande, A Ivanov, R Saleh Microelectronics Journal 36 (9), 833-845, 2005 | 71 | 2005 |
| Jitter models and measurement methods for high-speed serial interconnects A Kuo, T Farahmand, N Ou, S Tabatabaei, A Ivanov 2004 International Conferce on Test, 1295-1302, 2004 | 68 | 2004 |
