Segui
Dipanjan Roy
Titolo
Citata da
Citata da
Anno
DSP design protection in CE through algorithmic transformation based structural obfuscation
A Sengupta, D Roy, SP Mohanty, P Corcoran
IEEE Transactions on Consumer Electronics 63 (4), 467-476, 2017
612017
Triple-Phase Watermarking for Reusable IP Core Protection during Architecture Synthesis
A Sengupta, D Roy
IEEE Transactions on Computer Aided Design of Integrated Circuits & Systems …, 2017
452017
Antipiracy-Aware IP Chipset Design for CE Devices: A Robust Watermarking Approach [Hardware Matters]
A Sengupta, D Roy
IEEE Consumer Electronics Magazine 6 (2), 118-124, 2017
322017
Protecting IP core during architectural synthesis using HLT-based obfuscation
D Roy, A Sengupta
Electronics Letters 53 (13), 849-851, 2017
312017
Low cost functional obfuscation of reusable IP cores used in CE hardware through robust locking
A Sengupta, D Kachave, D Roy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2018
302018
Low-cost obfuscated JPEG CODEC IP core for secure CE hardware
A Sengupta, D Roy, SP Mohanty, P Corcoran
IEEE Transactions on Consumer Electronics 64 (3), 365-374, 2018
292018
Low overhead symmetrical protection of reusable IP core using robust fingerprinting and watermarking during high level synthesis
D Roy, A Sengupta
Future Generation Computer Systems 71, 89–101, 2017
232017
Intellectual property-based lossless image compression for camera systems [hardware matters]
A Sengupta, D Roy
IEEE Consumer Electronics Magazine 7 (1), 119-124, 2017
82017
Enhancing Saliency of an Object using Genetic Algorithm
R Pal, D Roy
14th Conference on Computer and Robot Vision, Edmonton, Canada, 2017
82017
Multilevel Watermark for Protecting DSP Kernel in CE Systems [Hardware Matters]
D Roy, A Sengupta
IEEE Consumer Electronics Magazine 8 (2), 100-102, 2019
52019
Reusable intellectual property core protection for both buyer and seller
A Sengupta, D Roy
Consumer Electronics (ICCE), 2018 IEEE International Conference on, 1-3, 2018
52018
Mathematical validation of HWT based lossless image compression
A Sengupta, D Roy
2017 IEEE International Symposium on Nanoelectronic and Information Systems …, 2017
52017
A framework for hardware efficient reusable IP core for grayscale image CODEC
A Sengupta, D Roy, SP Mohanty, P Corcoran
IEEE Access 6, 871-882, 2017
52017
Low cost optimized Trojan secured schedule at behavioral level for single and Nested loop control data flow graphs
A Sengupta, D Roy, S Bhadauria
Integration, the VLSI Journal, 2016
42016
Signature-free watermark for protecting digital signal processing cores used in CE devices [hardware matters]
P Sarkar, D Roy, A Sengupta, MK Naskar
IEEE Consumer Electronics Magazine 8 (1), 92-94, 2018
32018
Automated low cost scheduling driven watermarking methodology for modern CAD high-level synthesis tools
A Sengupta, D Roy
Advances in Engineering Software, 2017
32017
Securing Hardware Accelerator during High-level Synthesis
D Roy, SJ Shaik, S Sharma
2022 IEEE International Symposium on Hardware Oriented Security and Trust …, 2022
22022
Low-overhead robust RTL signature for DSP core protection: new paradigm for smart CE design
A Sengupta, D Roy, SP Mohanty
2019 IEEE International Conference on Consumer Electronics (ICCE), 1-6, 2019
22019
Multi-phase watermark for IP core protection
A Sengupta, D Roy
Consumer Electronics (ICCE), 2018 IEEE International Conference on, 1-3, 2018
22018
Securing Hardware Accelerator Against Reverse Engineering Attack
D Roy, SJ Shaik, S Sharma
2023 IEEE International Conference on Consumer Electronics (ICCE), 1-6, 2023
12023
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