High-performance fully depleted silicon nanowire (diameter/spl les/5 nm) gate-all-around CMOS devices N Singh, A Agarwal, LK Bera, TY Liow, R Yang, SC Rustagi, CH Tung, ...
IEEE Electron Device Letters 27 (5), 383-386, 2006
819 2006 Silicon nanowire arrays for ultrasensitive label-free detection of DNA Z Gao, A Agarwal, AD Trigg, N Singh, C Fang, CH Tung, KD Buddharaju
Solid-State Sensors, Actuators and Microsystems Conference, 2007 …, 2007
582 * 2007 Silicon nanowire arrays for label-free detection of DNA Z Gao, A Agarwal, AD Trigg, N Singh, C Fang, CH Tung, Y Fan, ...
Analytical chemistry 79 (9), 3291-3297, 2007
579 2007 Vertical Si-Nanowire R Gandhi, Z Chen, N Singh, K Banerjee, S Lee
IEEE Electron Device Letters 32 (4), 437-439, 2011
409 2011 Stacked silicon-germanium nanowire structure and method of forming the same GQ Lo, LK Bera, HS Nguyen, N Singh
US Patent App. 11/636,381, 2006
403 2006 DNA sensing by silicon nanowire: charge layer distance dependence GJ Zhang, G Zhang, JH Chua, RE Chee, EH Wong, A Agarwal, ...
Nano letters 8 (4), 1066-1070, 2008
358 2008 Vertical silicon-nanowire formation and gate-all-around MOSFET B Yang, KD Buddharaju, SHG Teo, N Singh, GQ Lo, DL Kwong
IEEE Electron Device Letters 29 (7), 791-794, 2008
278 2008 Excimer Laser-Annealed Dopant Segregated Schottky (ELA-DSS) Si Nanowire Gate-All-Around (GAA) pFET with Near Zero Effective Schottky Barrier Height (SBH) YK Chin, KL Pey, N Singh, GQ Lo, LH Tan, G Zhu, X Zhou, XC Wang, ...
Electron Devices Meeting (IEDM), 2009 IEEE International, 1-4, 2009
245 2009 Large area patterned magnetic nanostructures AO Adeyeye, N Singh
Journal of Physics D: Applied Physics 41 (15), 153001, 2008
230 2008 Si, SiGe nanowire devices by top–down technology and their applications N Singh, KD Buddharaju, SK Manhas, A Agarwal, SC Rustagi, GQ Lo, ...
IEEE Transactions on Electron Devices 55 (11), 3107-3118, 2008
219 2008 CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs With R Gandhi, Z Chen, N Singh, K Banerjee, S Lee
IEEE Electron Device Letters 32 (11), 1504-1506, 2011
218 2011 Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance N Singh, FY Lim, WW Fang, SC Rustagi, LK Bera, A Agarwal, CH Tung, ...
Electron Devices Meeting, 2006. IEDM'06. International, 1-4, 2006
215 2006 Demonstration of tunneling FETs based on highly scalable vertical silicon nanowires ZX Chen, HY Yu, N Singh, NS Shen, RD Sayanthan, GQ Lo, DL Kwong
IEEE Electron Device Letters 30 (7), 754-756, 2009
211 2009 Magnetic antidot nanostructures: effect of lattice geometry CC Wang, AO Adeyeye, N Singh
Nanotechnology 17 (6), 1629, 2006
207 2006 Z Fang, HY Yu, X Li, N Singh, GQ Lo, DL Kwong
IEEE Electron Device Letters 32 (4), 566-568, 2011
204 2011 Physical mechanisms of endurance degradation in TMO-RRAM B Chen, Y Lu, B Gao, YH Fu, FF Zhang, P Huang, YS Chen, LF Liu, ...
Electron Devices Meeting (IEDM), 2011 IEEE International, 12.3. 1-12.3. 4, 2011
176 2011 Collective spin modes in monodimensional magnonic crystals consisting of dipolarly coupled nanowires G Gubbiotti, S Tacchi, G Carlotti, N Singh, S Goolaup, AO Adeyeye, ...
Applied Physics Letters 90 (9), 092503, 2007
175 2007 Magnetostatic interaction in arrays of nanometric permalloy wires: A magneto-optic Kerr effect and a Brillouin light scattering study G Gubbiotti, S Tacchi, G Carlotti, P Vavassori, N Singh, S Goolaup, ...
Physical Review B 72 (22), 224413, 2005
158 2005 Chip-level thermoelectric power generators based on high-density silicon nanowire array prepared with top-down CMOS technology Y Li, K Buddharaju, N Singh, GQ Lo, SJ Lee
IEEE Electron Device Letters 32 (5), 674-676, 2011
151 2011 Partial frequency band gap in one-dimensional magnonic crystals M Kostylev, P Schrader, RL Stamps, G Gubbiotti, G Carlotti, AO Adeyeye, ...
Applied Physics Letters 92 (13), 132504, 2008
134 2008