| High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling S Bangsaruntip, GM Cohen, A Majumdar, Y Zhang, SU Engelmann, ... 2009 IEEE International Electron Devices Meeting (IEDM), 1-4, 2009 | 627 | 2009 |
| Gate-all-around silicon nanowire 25-stage CMOS ring oscillators with diameter down to 3 nm S Bangsaruntip, A Majumdar, GM Cohen, SU Engelmann, Y Zhang, ... 2010 symposium on VLSI technology, 21-22, 2010 | 319 | 2010 |
| Electrical integrity of state-of-the-art 0.13/spl mu/m SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication KW Guarini, AW Topol, M Ieong, R Yu, L Shi, MR Newport, DJ Frank, ... Digest. International Electron Devices Meeting,, 943-945, 2002 | 206 | 2002 |
| Universality of short-channel effects in undoped-body silicon nanowire MOSFETs S Bangsaruntip, GM Cohen, A Majumdar, JW Sleight IEEE Electron Device Letters 31 (9), 903-905, 2010 | 193 | 2010 |
| Nanowire field-effect transistors S Bangsaruntip, GM Cohen, KL Saenger US Patent 7,795,677, 2010 | 190 | 2010 |
| Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates GM Cohen US Patent 7,355,253, 2008 | 173 | 2008 |
| Method of forming vertical FET with nanowire channels and a silicided bottom contact GM Cohen, PM Solomon US Patent 7,446,025, 2008 | 143 | 2008 |
| Vertical FET with nanowire channels and a silicided bottom contact GM Cohen, PM Solomon US Patent 7,230,286, 2007 | 126 | 2007 |
| Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric S Bangsaruntip, G Cohen, MA Guillorn US Patent 9,029,834, 2015 | 125 | 2015 |
| Density scaling with gate-all-around silicon nanowire MOSFETs for the 10 nm node and beyond S Bangsaruntip, K Balakrishnan, SL Cheng, J Chang, M Brink, I Lauer, ... 2013 IEEE international electron devices meeting, 20.2. 1-20.2. 4, 2013 | 124 | 2013 |
| Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates GM Cohen US Patent 7,384,830, 2008 | 119 | 2008 |
| Two gates are better than one [double-gate MOSFET process] PM Solomon, KW Guarini, Y Zhang, K Chan, EC Jones, GM Cohen, ... IEEE circuits and devices magazine 19 (1), 48-62, 2003 | 116 | 2003 |
| Maskless process for suspending and thinning nanowires S Bangsaruntip, G Cohen, JW Sleight US Patent 7,884,004, 2011 | 115 | 2011 |
| Mixed orientation and mixed material semiconductor-on-insulator wafer GM Cohen, A Reznicek, KL Saenger, M Yang US Patent 7,125,785, 2006 | 115 | 2006 |
| Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques KK Chan, GM Cohen, Y Taur, HSP Wong US Patent 6,365,465, 2002 | 106 | 2002 |
| Triple-self-aligned, planar double-gate MOSFETs: devices and circuits KW Guarini, PM Solomon, Y Zhang, KK Chan, EC Jones, GM Cohen, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 105 | 2001 |
| Self-aligned silicide (salicide) process for low resistivity contacts to thin film silicon-on-insulator and bulk mosfets and for shallow junctions C Cabral, K Chan, G Cohen, C Lavoie, R Roy, P Solomon US Patent App. 10/989,639, 2006 | 100 | 2006 |
| Semiconductor-on-insulator lateral pin photodetector with a reflecting mirror and backside contact and method for forming the same GM Cohen, K Rim, DL Rogers, JD Schaub, M Yang US Patent 6,667,528, 2003 | 99 | 2003 |
| Enabling technologies for wafer-level bonding of 3D MEMS and integrated circuit structures AW Topol, BK Furman, KW Guarini, L Shi, GM Cohen, GF Walker 2004 Proceedings. 54th Electronic Components and Technology Conference (IEEE …, 2004 | 96 | 2004 |
| Method and system for providing a quality metric for improved process control D Kandel, G Cohen, D Klein, V Levinski, N Sapiens, A Shulman, ... US Patent 11,372,340, 2022 | 88 | 2022 |
