| A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang–Bang PLL With Digital Frequency-Error Recovery for Fast Locking A Santiccioli, M Mercandelli, L Bertulessi, A Parisi, D Cherniak, AL Lacaita, ... IEEE Journal of Solid-State Circuits 55 (12), 3349-3361, 2020 | 96 | 2020 |
| A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter M Mercandelli, A Santiccioli, A Parisi, L Bertulessi, D Cherniak, AL Lacaita, ... IEEE Journal of Solid-State Circuits 57 (2), 505-517, 2021 | 77 | 2021 |
| A 12.9-to-15.1-GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping SM Dartizio, F Tesolin, M Mercandelli, A Santiccioli, A Shehata, S Karman, ... IEEE Journal of Solid-State Circuits 57 (6), 1723-1735, 2021 | 21 | 2021 |
| 32.3 A 12.9-to-15.1 GHz digital PLL based on a bang-bang phase detector with adaptively optimized noise shaping achieving 107.6 fs integrated jitter M Mercandelli, A Santiccioli, SM Dartizio, A Shehata, F Tesolin, S Karman, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 445-447, 2021 | 16 | 2021 |
| 32.8 A 98.4 fs-jitter 12.9-to-15.1 GHz PLL-based LO phase-shifting system with digital background phase-offset correction for integrated phased arrays A Santiccioli, M Mercandelli, SM Dartizio, F Tesolin, S Karman, A Shehata, ... 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 456-458, 2021 | 10 | 2021 |
| 24.3 A 236-to-266GHz 4-Element Amplifier-Last Phased-Array Transmitter in 65nm CMOS C Wang, H Herdian, W Zheng, C Liu, J Mayeda, Y Liu, OA Yong, W Wang, ... 2024 IEEE International Solid-State Circuits Conference (ISSCC) 67, 415-417, 2024 | 9 | 2024 |
| A sub-THz full-duplex phased-array transceiver with self-interference cancellation and LO feedthrough suppression C Wang, I Abdo, C Liu, C da Gomez, J Mayeda, H Herdian, W Wang, X Fu, ... IEEE Journal of Solid-State Circuits, 2024 | 5 | 2024 |
| A D-Band Wideband Single-Ended Neutralized Up-Conversion Mixer with Controlled LO Feedthrough in 65nm CMOS C Wang, C Liu, H Herdian, A Shehata, J Mayeda, K Kunihiro, H Sakai, ... IEEE Solid-State Circuits Letters, 2024 | 2 | 2024 |
| A sub-THz full-duplex phased-array transceiver with self-interference cancellation and LO feedthrough suppression C Wang, I Abdo, C Liu, C Da Gomez, H Herdian, W Wang, X Fu, D You, ... 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and …, 2023 | 2 | 2023 |
| A new delta-sigma time-to-digital converter for low-jitter digital PLLs A SHEHATA Politecnico di Milano, 2018 | | 2018 |
