Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding SW Kim, F Fodor, N Heylen, S Iacovo, J De Vos, A Miller, G Beyer, ...
2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 216-222, 2020
93 2020 Reliable 50Gb/s silicon photonics platform for next-generation data center optical interconnects P Absil, K Croes, A Lesniewska, P De Heyn, Y Ban, B Snyder, J De Coster, ...
2017 IEEE International Electron Devices Meeting (IEDM), 34.2. 1-34.2. 4, 2017
53 2017 Demonstration of a collective hybrid die-to-wafer integration S Suhard, A Phommahaxay, K Kennes, P Bex, F Fodor, M Liebens, ...
2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 1315-1321, 2020
20 2020 Demonstration of a collective hybrid die-to-wafer integration using glass carrier S Suhard, K Kennes, P Bex, A Jourdain, L Teugels, E Walsby, C Bolton, ...
2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2064-2070, 2021
19 2021 New Cu “Bulge-Out” Mechanism Supporting SubMicron Scaling of Hybrid Wafer-to-Wafer Bonding J De Messemaeker, L Witters, B Zhang, YW Tsau, F Fodor, J De Vos, ...
2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), 109-113, 2023
17 2023 High density and high bandwidth chip-to-chip connections with 20μm pitch flip-chip on fan-out wafer level package D Velenis, A Phommahaxay, P Bex, F Fodor, EJ Marinissen, K Rebibis, ...
2018 International Wafer Level Packaging Conference (IWLPC), 1-5, 2018
16 2018 A fully automatic test system for characterizing large-array fine-pitch micro-bump probe cards EJ Marinissen, F Fodor, B De Wächter, J Kiesewetter, E Hill, K Smith
2017 International Test Conference in Asia (ITC-Asia), 144-149, 2017
13 2017 Solutions to multiple probing challenges for test access to multi-die stacked integrated circuits EJ Marinissen, F Fodor, A Podpod, M Stucchi, YR Jian, CW Wu
2018 IEEE International Test Conference (ITC), 1-10, 2018
10 2018 Multi-tier S Van Huylenbroeck, J De Vos, L Teugels, S Iacovo, F Fodor, A Miller, ...
2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 1057-1062, 2021
7 2021 Testing embedded toggle pattern generation through on-chip IR drop monitoring K Monta, L Kataselas, F Fodor, A Hatzopoulos, M Nagata, EJ Marinissen
2021 IEEE European Test Symposium (ETS), 1-4, 2021
3 2021 Process development and characterization of 3D multi-die stacking C Gerets, J Derakhshandeh, P Bex, M Lofrano, V Cherman, F Fodor, ...
2020 IEEE 8th Electronics System-Integration Technology Conference (ESTC), 1-6, 2020
3 2020 Leading-edge wide-I/O2 memory probing challenges: TPEG (TM) MEMS solution F Fodor, EJ Marinissen, D Acconcia, R Vallauri
3 2018 Automated probe-mark analysis for advanced probe technology characterization YR Jian, F Fodor, CW Wu, EJ Marinissen
IEEE Design & Test 38 (5), 82-89, 2021
2 2021 Accurate measurements of small resistances in vertical interconnects with small aspect ratios M Stucchi, F Fodor, EJ Marinissen
2020 IEEE European Test Symposium (ETS), 1-6, 2020
1 2020 Evaluation of advanced probe cards for large-array fine-pitch micro-bumps EJ Marinissen, F Fodor, B De Wachter, J Kiesewetter, K Smith, E Hill
1 2017 Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements K Monta, L Katselas, F Fodor, T Miki, A Hatzopoulos, M Nagata, ...
IEEE Design & Test 39 (5), 79-87, 2022
2022 Diagnosis of Switching-Induced IR Drop by On-Chip Voltage Monitors L Kataselas, F Fodor, A Hatzopoulos, M Nagata, EJ Marinissen
IEICE Technical Report; IEICE Tech. Rep. 121 (278), 83-86, 2021
2021 Probing complexities of 3D-stacked ICs–A test engineers' perspective F Fodor, B De Wachter, A Podpod, M Stucchi, EJ Marinissen
2020 Automated Probe-Mark Analysis CW Wu, YR Jian, F Fodor, EJ Marinissen
Semiconductor Wafer Test Workshop (SWTW), 2018
2018 Automated probe mark analysis YR Rong, CW Wu, F Fodor, EJ Marinissen
2018