Low voltage analog circuit design techniques: A tutorial S Yan, E Sanchez-Sinencio
IEICE Transactions on Fundamentals of Electronics, Communications and …, 2000
396 2000 A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth S Yan, E Sánchez-Sinencio
IEEE Journal of Solid-State Circuits 39 (1), 75-86, 2004
379 2004 A 32 mW 1.25 GS/s 6b 2b/Step SAR ADC in 0.13 Z Cao, S Yan, Y Li
IEEE journal of solid-state circuits 44 (3), 862-873, 2009
190 2009 A 32mw 1.25 gs/s 6b 2b/step sar adc in 0.13 μm cmos Z Cao, S Yan, Y Li
2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008
144 2008 A 2.7-mW 2-MHz Continuous-Time T Song, Z Cao, S Yan
IEEE Journal of Solid-State Circuits 43 (2), 330-341, 2008
117 2008 An RC time constant auto-tuning structure for high linearity continuous-time/spl Sigma//spl Delta/modulators and active filters B Xia, S Yan, E Sánchez-Sinencio
IEEE Transactions on Circuits and Systems I: Regular Papers 51 (11), 2179-2188, 2004
103 2004 Capacitive isolation circuitry with improved common mode detector Z Dong, S Yan, A Thomsen, WWK Tang, KY Leung
US Patent 7,902,627, 2011
96 2011 Capacitive isolation circuitry Z Dong, S Yan, A Thomsen, WWK Tang, KY Leung
US Patent 8,198,951, 2012
82 2012 A 0.4 ps-RMS-jitter 1–3 GHz ring-oscillator PLL using phase-noise preamplification Z Cao, Y Li, S Yan
IEEE journal of solid-state circuits 43 (9), 2079-2089, 2008
64 2008 Feedforward reversed nested Miller compensation techniques for three-stage amplifiers F Zhu, S Yan, J Hu, E Sánchez-Sinencio
2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2575-2578, 2005
51 2005 Constant-g/sub m/techniques for rail-to-rail CMOS amplifier input stages: a comparative study S Yan, J Hu, T Song, E Sánchez-Sinencio
2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2571-2574, 2005
48 2005 A hybrid SAR-VCO ΔΣ ADC with first-order noise shaping A Sanyal, K Ragab, L Chen, TR Viswanathan, S Yan, N Sun
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014
45 2014 Linear regulator having a closed loop frequency response based on a decoupling capacitance S Yan, A Thomsen, P Kallam
US Patent 9,625,925, 2017
36 2017 A constant-g/sub m/rail-to-rail op amp input stage using dynamic current scaling technique S Yan, J Hu, T Song, E Sanchez-Sinencio
2005 IEEE International Symposium on Circuits and Systems (ISCAS), 2567-2570, 2005
28 2005 Method and apparatus for calibration of successive approximation register analog-to-digital converters Y Zhou, C Daigle, S Yan, M Elsayed
US Patent 9,041,569, 2015
27 2015 A mixed signal (analog-digital) integrator design MD Bryant, S Yan, R Tsang, B Fernandez, KK Kumar
IEEE Transactions on Circuits and Systems I: Regular Papers 59 (7), 1409-1417, 2012
27 2012 A 14 mW 2.5 MS/s 14 bit Z Cao, T Song, S Yan
IEEE journal of solid-state circuits 42 (10), 2169-2179, 2007
25 2007 An uncalibrated 2MHz, 6mW, 63.5 dB SNDR discrete-time input VCO-based ΔΣ ADC J Hamilton, S Yan, TR Viswanathan
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 1-4, 2012
24 2012 A Discrete-Time Input J Hamilton, S Yan, TR Viswanathan
IEEE Transactions on Circuits and Systems II: Express Briefs 57 (11), 848-852, 2010
22 2010 A Robust Rail-to-Rail Input Stage with Constant-gm and Constant Slew Rate Using a Novel Level Shifter T Song, S Yan
2007 IEEE International Symposium on Circuits and Systems (ISCAS), 477-480, 2007
21 2007