| An analytical model for tunnel barrier modulation in triple metal double gate TFET N Bagga, SK Sarkar IEEE transactions on electron devices 62 (7), 2136-2142, 2015 | 114 | 2015 |
| Surface potential and drain current analytical model of gate all around triple metal TFET N Bagga, S Dasgupta IEEE Transactions on Electron Devices 64 (2), 606-613, 2017 | 85 | 2017 |
| Demonstration of a novel two source region tunnel FET N Bagga, A Kumar, S Dasgupta IEEE Transactions on Electron Devices 64 (12), 5256-5262, 2017 | 76 | 2017 |
| Design optimization of three-stacked nanosheet FET from self-heating effects perspective S Rathore, RK Jaisawal, PN Kondekar, N Bagga IEEE Transactions on Device and Materials Reliability 22 (3), 396-402, 2022 | 43 | 2022 |
| Compact 2D modeling and drain current performance analysis of a work function engineered double gate tunnel field effect transistor S Sarkhel, N Bagga, SK Sarkar Journal of Computational Electronics 15, 104-114, 2016 | 37 | 2016 |
| Dielectric modulated GaAs1− x Sb X FinFET as a label-free biosensor: Device proposal and investigation A Dixit, DP Samajdar, N Bagga Semiconductor Science and Technology 36 (9), 095033, 2021 | 28 | 2021 |
| Assessing the analog/RF and linearity performances of FinFET using high threshold voltage techniques RK Jaisawal, S Rathore, PN Kondekar, S Yadav, B Awadhiya, ... Semiconductor Science and Technology 37 (5), 055010, 2022 | 27 | 2022 |
| Demonstration of a nanosheet FET with high thermal conductivity material as buried oxide: Mitigation of self-heating effect S Rathore, RK Jaisawal, PN Kondekar, N Bagga IEEE Transactions on Electron Devices 70 (4), 1970-1976, 2023 | 25 | 2023 |
| A novel negative capacitance FinFET with ferroelectric spacer: proposal and investigation V Chauhan, DP Samajdar, N Bagga, A Dixit IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 68 …, 2021 | 24 | 2021 |
| A novel twofold tunnel FET with reduced miller capacitance: proposal and investigation N Bagga, N Chauhan, D Gupta, S Dasgupta IEEE Transactions on Electron Devices 66 (7), 3202-3208, 2019 | 22 | 2019 |
| Trap and self-heating effect based reliability analysis to reveal early aging effect in nanosheet FET S Rathore, RK Jaisawal, PN Kondekar, N Bagga Solid-State Electronics 200, 108546, 2023 | 20 | 2023 |
| Role of temperature on linearity and analog/RF performance merits of a negative capacitance FinFET RK Jaisawal, S Rathore, N Gandhi, PN Kondekar, N Bagga Semiconductor Science and Technology 37 (11), 115003, 2022 | 18 | 2022 |
| Reliability of TCAD study for HfO2-doped Negative capacitance FinFET with different Material-Specific dopants RK Jaisawal, S Rathore, PN Kondekar, N Bagga Solid-State Electronics 199, 108531, 2023 | 17 | 2023 |
| Negative-to-positive differential resistance transition in ferroelectric FET: physical insight and utilization in analog circuits N Chauhan, N Bagga, S Banchhor, A Datta, S Dasgupta, A Bulusu IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control 69 …, 2021 | 16 | 2021 |
| BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective N Chauhan, N Bagga, S Banchhor, C Garg, A Sharma, A Datta, ... Nanotechnology 33 (8), 085203, 2021 | 15 | 2021 |
| Performance investigation of a novel GaAs1-xSbx-on-insulator (GASOI) FinFET: Role of interface trap charges and hetero dielectric A Dixit, DP Samajdar, N Bagga, DS Yadav Materials Today Communications 26, 101964, 2021 | 15 | 2021 |
| Recent research trends in gate engineered tunnel FET for improved current behavior by subduing the ambipolar effects: A review N Bagga, S Sarkhel, SK Sarkar International Conference on Computing, Communication & Automation, 1264-1267, 2015 | 15 | 2015 |
| Self-heating and interface traps assisted early aging revelation and reliability analysis of negative capacitance FinFET RK Jaisawal, S Rathore, N Gandhi, PN Kondekar, S Banchhor, ... 2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2023 | 14 | 2023 |
| Demonstration of a novel tunnel FET with channel sandwiched by drain N Bagga, N Chauhan, S Banchhor, D Gupta, S Dasgupta Semiconductor Science and Technology 35 (1), 015008, 2019 | 14 | 2019 |
| Traps based reliability barrier on performance and revealing early ageing in negative capacitance FET A Gupta, G Bajpai, P Singhal, N Bagga, O Prakash, S Banchhor, ... 2021 IEEE International Reliability Physics Symposium (IRPS), 1-6, 2021 | 12 | 2021 |
Sudeb DasguptaDepartment of Electronics and Communication Engineering, IIT RoorkeeEmail verificata su iitr.ac.in