| Intercalation doped multilayer-graphene-nanoribbons for next-generation interconnects J Jiang, J Kang, W Cao, X Xie, H Zhang, JH Chu, W Liu, K Banerjee Nano letters 17 (3), 1482-1488, 2017 | 162 | 2017 |
| Ultimate monolithic-3D integration with 2D materials: rationale, prospects, and challenges J Jiang, K Parto, W Cao, K Banerjee IEEE Journal of the Electron Devices Society 7, 878-887, 2019 | 112 | 2019 |
| On-chip intercalated-graphene inductors for next-generation radio frequency electronics J Kang, Y Matsumoto, X Li, J Jiang, X Xie, K Kawamoto, M Kenmoku, ... Nature Electronics 1 (1), 46-51, 2018 | 104 | 2018 |
| 2-D layered materials for next-generation electronics: Opportunities and challenges W Cao, J Jiang, X Xie, A Pal, JH Chu, J Kang, K Banerjee IEEE Transactions on Electron Devices 65 (10), 4109-4121, 2018 | 99 | 2018 |
| Designing band-to-band tunneling field-effect transistors with 2D semiconductors for next-generation low-power VLSI W Cao, J Jiang, J Kang, D Sarkar, W Liu, K Banerjee 2015 IEEE International Electron Devices Meeting (IEDM), 12.3. 1-12.3. 4, 2015 | 41 | 2015 |
| CMOS-compatible doped-multilayer-graphene interconnects for next-generation VLSI J Jiang, JH Chu, K Banerjee 2018 IEEE International Electron Devices Meeting (IEDM), 34.5. 1-34.5. 4, 2018 | 30 | 2018 |
| Characterization of self-heating and current-carrying capacity of intercalation doped graphene-nanoribbon interconnects J Jiang, J Kang, K Banerjee 2017 IEEE International Reliability Physics Symposium (IRPS), 6B-1.1-6B-1.6, 2017 | 25 | 2017 |
| All-carbon interconnect scheme integrating graphene-wires and carbon-nanotube-vias J Jiang, J Kang, JH Chu, K Banerjee 2017 IEEE International Electron Devices Meeting (IEDM), 14.3. 1-14.3. 4, 2017 | 19 | 2017 |
| Monolithic-3D integration with 2D materials: Toward ultimate vertically-scaled 3D-ICs J Jiang, K Parto, W Cao, K Banerjee 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2018 | 17 | 2018 |
| Demonstration of CMOS-compatible multi-level graphene interconnects with metal vias K Agashiwala, J Jiang, K Parto, D Zhang, CH Yeh, K Banerjee IEEE Transactions on Electron Devices 68 (4), 2083-2091, 2021 | 15 | 2021 |
| Two-dimensional materials enabled next-generation low-energy compute and connectivity A Pal, K Agashiwala, J Jiang, D Zhang, T Chavan, A Kumar, CH Yeh, ... MRS Bulletin 46 (12), 1211-1228, 2021 | 14 | 2021 |
| An ultra energy-efficient hardware platform for neuromorphic computing enabled by 2D-TMD tunnel-FETs A Pal, Z Chai, J Jiang, W Cao, M Davies, V De, K Banerjee Nature Communications 15 (1), 3392, 2024 | 5 | 2024 |
| 2018 IEEE SOI‐3D‐Subthreshold Microelectronics Technology Unified Conf.(S3S) J Jiang, K Parto, W Cao, K Banerjee IEEE, 2018 | 4 | 2018 |
| Reliability and performance of CMOS-compatible multi-level graphene interconnects incorporating vias K Agashiwala, J Jiang, CH Yeh, K Parto, D Zhang, K Banerjee 2020 IEEE International Electron Devices Meeting (IEDM), 31.1. 1-31.1. 4, 2020 | 3 | 2020 |
| Can kinetic inductance in low-dimensional materials enable a new generation of RF-electronics? K Agashiwala, A Pal, W Cao, J Jiang, K Banerjee 2018 IEEE International Electron Devices Meeting (IEDM), 24.4. 1-24.4. 4, 2018 | 3 | 2018 |
| Cmos-compatible graphene structures, interconnects and fabrication methods K Banerjee, J Jiang, K Agashiwala US Patent App. 18/252,459, 2024 | | 2024 |
Kaustav BanerjeeUC Santa Barbara, Stanford University, UC BerkeleyEmail verificata su ece.ucsb.edu