| 8 Gb 3-D DDR3 DRAM using through-silicon-via technology U Kang, HJ Chung, S Heo, DH Park, H Lee, JH Kim, SH Ahn, SH Cha, ... IEEE Journal of Solid-State Circuits 45 (1), 111-119, 2009 | 686 | 2009 |
| Semiconductor package having memory devices stacked on logic device K Uk-Song US Patent 7,834,450, 2010 | 348 | 2010 |
| A high-speed capacitive humidity sensor with on-chip thermal reset U Kang, KD Wise IEEE Transactions on Electron Devices 47 (4), 702-710, 2000 | 281 | 2000 |
| Co-architecting controllers and DRAM to enhance DRAM process scaling U Kang, HS Yu, C Park, H Zheng, J Halbert, K Bains, S Jang, JS Choi The memory forum 14, 2014 | 210 | 2014 |
| Stacked memory device K Uk-Song, JB Lee, H Chung US Patent 7,999,367, 2011 | 155 | 2011 |
| Multi-chip memory device with stacked memory chips, method of stacking memory chips, and method of controlling operation of multi-chip package memory H Chung, JB Lee, K Uk-Song US Patent 7,830,692, 2010 | 134 | 2010 |
| Semiconductor device having stacked structure including through-silicon-vias and method of testing the same K Uk-Song US Patent App. 13/312,000, 2012 | 108 | 2012 |
| A 1.2 V 20 nm 307 GB/s HBM DRAM with at-speed wafer-level IO test scheme and adaptive refresh considering temperature distribution K Sohn, WJ Yun, R Oh, CS Oh, SY Seo, MS Park, DH Shin, WC Jung, ... IEEE Journal of Solid-State Circuits 52 (1), 250-260, 2016 | 105 | 2016 |
| Semiconductor memory device K Uk-Song, YH Jun, JS Choi US Patent 8,885,380, 2014 | 100 | 2014 |
| Memory system H Yu, K Uk-Song, CW Park, JS Choi, HS Hwang US Patent App. 13/604,308, 2013 | 95 | 2013 |
| Memory modules and memory systems JP Son, K Uk-Song, CW Park, YS Sohn US Patent 9,087,614, 2015 | 76 | 2015 |
| Method and apparatus for refreshing and data scrubbing memory device K Uk-Song, H Yu, CW Park US Patent 9,053,813, 2015 | 69 | 2015 |
| Dynamic random access memory device and method of determining refresh cycle thereof SS Pyo, K Uk-Song US Patent 7,894,282, 2011 | 69 | 2011 |
| Memory device with flexible internal data write control circuitry U Kang, CE Cox US Patent 10,249,351, 2019 | 67 | 2019 |
| Semiconductor memory device having adjustable refresh period, memory system comprising same, and method of operating same K Uk-Song US Patent 9,153,294, 2015 | 66 | 2015 |
| Increased redundancy in multi-device memory package to improve reliability W Wu, U Kang, H Alameer, R Agarwal, KE Criss, JB Halbert US Patent App. 15/814,336, 2018 | 47 | 2018 |
| Stacked memory module and system K Uk-Song, H Chung, JS Choi, H Lee US Patent 8,031,505, 2011 | 47 | 2011 |
| Multi-chip package (MCP) having three dimensional mesh-based power distribution network, and power distribution method of the MCP H Lee, KW Lee, K Uk-Song US Patent App. 12/458,124, 2010 | 42 | 2010 |
| Memory modules and memory systems K Uk-Song, CW Park, H Yu, JP Son US Patent 9,558,805, 2017 | 41 | 2017 |
| Semiconductor package having memory devices stacked on logic device K Uk-Song US Patent 8,253,244, 2012 | 34 | 2012 |
