| Nickel vs. Cobalt Silicide integration for sub-50nm CMOS B Froment, M Muller, H Brut, R Pantel, V Carron, H Achard, A Halimaoui, ... ESSDERC'03. 33rd Conference on European Solid-State Device Research, 2003 …, 2003 | 264 | 2003 |
| High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond Q Liu, M Vinet, J Gimbert, N Loubet, R Wacquez, L Grenouillet, Y Le Tiec, ... 2013 IEEE International Electron Devices Meeting, 9.2. 1-9.2. 4, 2013 | 123 | 2013 |
| Passivation issues in Active Pixel CMOS Image Sensors J Regolini, D Benoit, P Morin WODIM, Workshop on Dielectrics in Microelectronics, 2006 | 90 | 2006 |
| Defect-free strain relaxed buffer layer P Morin, K Cheng, J Fronheiser, X Cai, J Li, S Mochizuki, R Xie, H He, ... US Patent App. 14/588,221, 2016 | 84 | 2016 |
| First monolithic integration of 3d complementary fet (cfet) on 300mm wafers S Subramanian, M Hosseini, T Chiarella, S Sarkar, P Schuddinck, ... 2020 Ieee Symposium on Vlsi Technology, 1-2, 2020 | 75 | 2020 |
| Hydrogen desorption and diffusion in PECVD silicon nitride. Application to passivation of CMOS active pixel sensors D Benoit, J Regolini, P Morin INFOS, Conference of Insulating Films on Semiconductors, 2007 | 68 | 2007 |
| Stress memorization technique (SMT) optimization for 45nm CMOS C Ortolland, P Morin, C Chaton, E Mastromatteo, C Populaire, S Orain, ... 2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers., 78-79, 2006 | 62 | 2006 |
| A functional 0.69/spl mu/m/sup 2/embedded 6T-SRAM bit cell for 65 nm CMOS platform F Arnaud, F Boeuf, F Salvetti, D Lenoble, F Wacquant, C Regnier, P Morin, ... 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2003 | 60 | 2003 |
| A conventional 45nm CMOS node low-cost platform for general purpose and low power applications F Boeuf, F Arnaud, MT Basso, D Sotta, F Wacquant, J Rosa, ... IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004 …, 2004 | 58 | 2004 |
| A comparison of the mechanical stability of silicon nitride films deposited with various techniques P Morin, G Raymond, D Benoit, P Maury, R Beneyton Applied surface science 260, 69-72, 2012 | 56 | 2012 |
| Method to induce strain in finFET channels from an adjacent region P Morin, N Loubet US Patent 9,099,559, 2015 | 50 | 2015 |
| Wafer-scale integration of double gated WS2-transistors in 300mm Si CMOS fab I Asselberghs, Q Smets, T Schram, B Groven, D Verreck, A Afzalian, ... 2020 IEEE International Electron Devices Meeting (IEDM), 40.2. 1-40.2. 4, 2020 | 47 | 2020 |
| Engineering wafer-scale epitaxial two-dimensional materials through sapphire template screening for advanced high-performance nanoelectronics Y Shi, B Groven, J Serron, X Wu, A Nalin Mehta, A Minj, S Sergeant, ... ACS nano 15 (6), 9482-9494, 2021 | 46 | 2021 |
| Three dimensional imaging and analysis of a single nano-device at the ultimate scale using correlative microscopy techniques A Grenier, S Duguay, JP Barnes, R Serra, N Rolland, G Audoit, P Morin, ... Applied Physics Letters 106 (21), 2015 | 46 | 2015 |
| Low cost 65nm cmos platform for low power & general purpose applications F Arnaud, B Duriez, B Tavel, L Pain, J Todeschini, M Jurdit, Y Laplanche, ... Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 10-11, 2004 | 46 | 2004 |
| Method to induce strain in 3-D microfabricated structures N Loubet, P Morin US Patent 8,952,420, 2015 | 42 | 2015 |
| 0.248/spl mu/m/sup 2/and 0.334/spl mu/m/sup 2/conventional bulk 6T-SRAM bit-cells for 45nm node low cost-general purpose applications F Boeuf, F Arnaud, C Boccaccio, F Salvetti, J Todeschini, L Pain, M Jurdit, ... Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005., 130-131, 2005 | 39 | 2005 |
| Buried power rail integration with FinFETs for ultimate CMOS scaling A Gupta, OV Pedreira, G Arutchelvan, H Zahedmanesh, K Devriendt, ... IEEE Transactions on Electron Devices 67 (12), 5349-5354, 2020 | 38 | 2020 |
| Method to form strained channel in thin box SOI structures by elastic strain relaxation of the substrate P Morin US Patent 9,236,474, 2016 | 38 | 2016 |
| FDSOI CMOS Devices Featuring Dual Strained Channel and Thin BOX Extendable to the 10nm Node Q Liu, P ...Morin, ... IEDM, 2014 | 38 | 2014 |
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