| Spalling methods to form multi-junction photovoltaic structure SW Bedell, DK Sadana, D Shahrjerdi US Patent 8,927,318, 2015 | 493 | 2015 |
| Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys B Hekmatshoar-Tabari, M Hopstaken, DG Park, DK Sadana, GG Shahidi, ... US Patent 8,778,448, 2014 | 473 | 2014 |
| Method of stabilizing hydrogenated amorphous silicon and amorphous hydrogenated silicon alloys B Hekmatshoar-Tabari, M Hopstaken, DG Park, DK Sadana, GG Shahidi, ... US Patent 9,099,585, 2015 | 471 | 2015 |
| Principle of direct van der Waals epitaxy of single-crystalline films on epitaxial graphene J Kim, C Bayram, H Park, CW Cheng, C Dimitrakopoulos, JA Ott, ... Nature communications 5 (1), 4836, 2014 | 428 | 2014 |
| Efficient and bright organic light-emitting diodes on single-layer graphene electrodes N Li, S Oida, GS Tulevski, SJ Han, JB Hannon, DK Sadana, TC Chen Nature communications 4 (1), 2294, 2013 | 415 | 2013 |
| Fin FET devices from bulk semiconductor and method for forming DM Fried, EJ Nowak, BA Rainey, DK Sadana US Patent 6,642,090, 2003 | 376 | 2003 |
| Method of preventing surface roughening during hydrogen pre-bake of SiGe substrates using chlorine containing gases H Chen, D Mocuta, R Murphy, S Bedell, D Sadana US Patent App. 10/751,207, 2005 | 367 | 2005 |
| Epitaxial lift-off process for gallium arsenide substrate reuse and flexible electronics CW Cheng, KT Shiu, N Li, SJ Han, L Shi, DK Sadana Nature communications 4 (1), 1577, 2013 | 357 | 2013 |
| SOI CMOS structure W Chen, DK Sadana, Y Taur US Patent 5,767,549, 1998 | 357 | 1998 |
| Low temperature epitaxy of a semiconductor alloy including silicon and germanium employing a high order silane precursor PD Brabant, K Chung, H He, DK Sadana, M Shinriki US Patent 9,218,962, 2015 | 319 | 2015 |
| Method of preventing surface roughening during hydrogen prebake of SiGe substrates H Chen, DM Mocuta, RJ Murphy, SW Bedell, DK Sadana US Patent 6,958,286, 2005 | 303 | 2005 |
| Heterojunction III-V photovoltaic cell fabrication SW Bedell, NS Cortes, KE Fogel, D Sadana, G Shahidi, D Shahrjerdi US Patent 8,802,477, 2014 | 300 | 2014 |
| Thin semiconductor-on-insulator mosfet with co-integrated silicon, silicon germanium and silicon doped with carbon channels TN Adam, SW Bedell, K Cheng, BB Doris, A Khakifirooz, A Reznicek, ... US Patent App. 13/280,850, 2013 | 286 | 2013 |
| Techniques for Layer Transfer Processing S Bedell, K Fogel, B Furman, S Purushothaman, D Sadana, A Topol US Patent App. 11/840,389, 2007 | 273 | 2007 |
| Layer-resolved graphene transfer via engineered strain layers J Kim, H Park, JB Hannon, SW Bedell, K Fogel, DK Sadana, ... Science 342 (6160), 833-836, 2013 | 269 | 2013 |
| Low-temperature selective epitaxial growth of silicon for device integration B Hekmatshoar-Tabari, A Khakifirooz, A Reznicek, DK Sadana, ... US Patent App. 14/711,403, 2015 | 252 | 2015 |
| Techniques for layer transfer processing S Bedell, K Fogel, B Furman, S Purushothaman, D Sadana, A Topol US Patent App. 10/685,636, 2005 | 252 | 2005 |
| Kerf-less removal of Si, Ge, and III–V layers by controlled spalling to enable low-cost PV technologies SW Bedell, D Shahrjerdi, B Hekmatshoar, K Fogel, PA Lauro, JA Ott, ... IEEE Journal of Photovoltaics 2 (2), 141-147, 2012 | 228 | 2012 |
| Low cost soi substrates for monolithic solar cells SW Bedell, JP De Souza, KE Fogel, HJ Hovel, DA Inns, J Kim, DK Sadana, ... US Patent App. 12/436,249, 2010 | 196 | 2010 |
| Silicon-on-insulator vertical array device trench capacitor DRAM CJ Radens, GB Bronner, TC Chen, B Davari, JA Mandelman, D Moy, ... US Patent 6,566,177, 2003 | 193 | 2003 |
Ning LiIBM T. J. Watson Research CenterEmail verificata su us.ibm.com