| Charge storage structure formation in transistor with vertical channel region MK Orlowski US Patent 7,535,060, 2009 | 448 | 2009 |
| Carrier transport near the Si/SiO2 interface of a MOSFET W Hänsch, T Vogelsang, R Kircher, M Orlowski Solid-State Electronics 32 (10), 839-849, 1989 | 263 | 1989 |
| Process for forming an electrically programmable read-only memory cell MK Orlowski, KM Chang US Patent 5,705,415, 1998 | 191 | 1998 |
| A statistical polishing pad model for chemical-mechanical polishing TK Yu, CC Yu, M Orlowski Proceedings of IEEE International Electron Devices Meeting, 865-868, 1993 | 172 | 1993 |
| Split-gate vertically oriented EEPROM device and process M Orlowski, KT Chang, KE Witek, J Fitch US Patent 6,433,382, 2002 | 163 | 2002 |
| A model for phosphorus segregation at the silicon-silicon dioxide interface F Lau, L Mader, C Mazure, C Werner, M Orlowski Applied Physics A 49, 671-675, 1989 | 142 | 1989 |
| Semiconductor device structure and method therefor TR White, AL Barr, BY Nguyen, MK Orlowski, MG Sadaka, VY Thean US Patent 7,226,833, 2007 | 126 | 2007 |
| Unified model for impurity diffusion in silicon M Orlowski Applied physics letters 53 (14), 1323-1325, 1988 | 114 | 1988 |
| Method of forming a transistor having multiple channels MK Orlowski, L Mathew US Patent 6,921,700, 2005 | 106 | 2005 |
| Volatile resistive switching in Cu/TaOx/δ-Cu/Pt devices T Liu, M Verma, Y Kang, M Orlowski Applied Physics Letters 101 (7), 2012 | 93 | 2012 |
| GeSOI transistor with low junction current and low junction capacitance and method for making the same M Orlowski, S Goktepeli, CL Liu US Patent 7,221,006, 2007 | 86 | 2007 |
| Semiconductor structure with different lattice constant materials and method for forming the same CL Liu, AL Barr, JM Grant, BY Nguyen, MK Orlowski, TA Stephens, ... US Patent 6,831,350, 2004 | 78 | 2004 |
| Submicron short channel effects due to gate reoxidation induced lateral interstitial diffusion M Orlowski, C Mazure, F Lau 1987 International Electron Devices Meeting, 632-635, 1987 | 78 | 1987 |
| Field effect transistor having a gate dielectric with variable thickness CA Mazure, MK Orlowski US Patent 5,314,834, 1994 | 72 | 1994 |
| Low RC product transistors in SOI semiconductor process AL Barr, OO Adetutu, BY Nguyen, MK Orlowski, MG Sadaka, VY Thean, ... US Patent 7,037,795, 2006 | 69 | 2006 |
| Semiconductor fabrication process employing stress inducing source drain structures with graded impurity concentration MK Orlowski, VH Adams, CL Liu, MW Stoker US Patent 7,238,580, 2007 | 67 | 2007 |
| Dual surface SOI by lateral epitaxial overgrowth BA Winstead, O Zia, MG Sadaka, MK Orlowski US Patent 7,435,639, 2008 | 63 | 2008 |
| Multi-channel transistor structure and method of making thereof MK Orlowski US Patent 7,354,831, 2008 | 55 | 2008 |
| Method of recrystallizing an amorphous region of a semiconductor WJ Taylor Jr, M Orlowski, DC Gilmer, PV Alluri, CC Hobbs, MJ Rendon, ... US Patent 6,573,160, 2003 | 55 | 2003 |
| Fully-depleted SOI devices with TaSiN gate, HfO2 gate dielectric, and elevated source/drain extensions A Vandooren, A Barr, L Mathew, TR White, S Egley, D Pham, M Zavala, ... IEEE Electron Device Letters 24 (5), 342-344, 2003 | 51 | 2003 |
Yuhong KangNanoSonic, Inc.Email verificata su nanosonic.com
