| A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size S Natarajan, M Agostinelli, S Akbar, M Bost, A Bowonder, V Chikarmane, ... 2014 IEEE International Electron Devices Meeting, 3.7. 1-3.7. 3, 2014 | 764 | 2014 |
| A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2SRAM cell size S Natarajan, M Agostinelli, S Akbar, M Bost, A Bowonder, V Chikarmane, ... 2014 IEEE International Electron Devices Meeting, 3.7. 1-3.7. 3, 2014 | 764 | 2014 |
| A 4.6GHz 162Mb SRAM design in 22nm tri-gate CMOS technology with integrated active VMIN-enhancing assist circuitry E Karl, Y Wang, YG Ng, Z Guo, F Hamzaoglu, U Bhattacharya, K Zhang, ... 2012 IEEE International Solid-State Circuits Conference, 230-232, 2012 | 232 | 2012 |
| Compact in-situ sensors for monitoring negative-bias-temperature-instability effect and oxide degradation E Karl, P Singh, D Blaauw, D Sylvester 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 158 | 2008 |
| Elastic: An adaptive self-healing architecture for unpredictable silicon D Sylvester, D Blaauw, E Karl IEEE Design & Test of Computers 23 (6), 484-490, 2006 | 150 | 2006 |
| A 14 nm SoC platform technology featuring 2nd generation Tri-Gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 um2 SRAM cells, optimized for … CH Jan, F Al-Amoody, HY Chang, T Chang, YW Chen, N Dias, W Hafez, ... 2015 Symposium on VLSI Technology (VLSI Technology), T12-T13, 2015 | 104 | 2015 |
| A 32nm High-k metal gate SRAM with adaptive dynamic stability enhancement for low-voltage operation H Nho, P Kolar, F Hamzaoglu, Y Wang, E Karl, YG Ng, U Bhattacharya, ... Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2010 …, 2010 | 99* | 2010 |
| Reliability modeling and management in dynamic microprocessor-based systems E Karl, D Blaauw, D Sylvester, T Mudge Proceedings of the 43rd annual Design Automation Conference, 1057-1060, 2006 | 96 | 2006 |
| 22FFL: A high performance and ultra low power FinFET technology for mobile and RF applications B Sell, B Bigwood, S Cha, Z Chen, P Dhage, P Fan, M Giraud-Carrier, ... 2017 IEEE International Electron Devices Meeting (IEDM), 29.4. 1-29.4. 4, 2017 | 87 | 2017 |
| A 4.6 GHz 162 Mb SRAM design in 22 nm tri-gate CMOS technology with integrated read and write assist circuitry E Karl, Y Wang, YG Ng, Z Guo, F Hamzaoglu, M Meterelliyoz, J Keane, ... IEEE Journal of Solid-State Circuits 48 (1), 150-158, 2012 | 76 | 2012 |
| Multi-mechanism reliability modeling and management in dynamic systems E Karl, D Blaauw, D Sylvester, T Mudge IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (4), 476-487, 2008 | 73 | 2008 |
| A 23.6-Mb/mm² SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications Z Guo, D Kim, S Nalam, J Wiedemer, X Wang, E Karl IEEE Journal of Solid-State Circuits, 1-7, 2018 | 69 | 2018 |
| A 23.6-Mb/mm² SRAM in 10-nm FinFET Technology With Pulsed-pMOS TVC and Stepped-WL for Low-Voltage Applications Z Guo, D Kim, S Nalam, J Wiedemer, X Wang, E Karl IEEE Journal of Solid-State Circuits, 1-7, 2018 | 69 | 2018 |
| Dynamic nbti management using a 45 nm multi-degradation sensor P Singh, E Karl, D Sylvester, D Blaauw IEEE Transactions on Circuits and Systems I: Regular Papers 58 (9), 2026-2037, 2011 | 68 | 2011 |
| Ponte Vecchio: A Multi-Tile 3D Stacked Processor for Exascale Computing W Gomes, A Koker, P Stover, D Ingerly, S Siers, S Venkataraman, C Pelto, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 42-44, 2022 | 65 | 2022 |
| Compact degradation sensors for monitoring NBTI and oxide degradation P Singh, E Karl, D Blaauw, D Sylvester IEEE Transactions on Very Large Scale Integration (VLSI) Systems 20 (9 …, 2011 | 64 | 2011 |
| A 0.6V 1.5 GHz 84Mb SRAM design in 14nm FinFET CMOS technology E Karl, Z Guo, JW Conary, JL Miller, YG Ng, S Nalam, D Kim, J Keane, ... Solid-State Circuits Conference-(ISSCC), 2015 IEEE International, 1-3, 2015 | 63* | 2015 |
| A 5.6 Mb/mm2 1R1W 8T SRAM arrays operating down to 560mV utilizing small-signal sensing with charge-shared bitline and asymmetric sense amplifier in 14nm FinFET CMOS technology J Keane, J Kulkarni, KH Koo, S Nalam, Z Guo, E Karl, K Zhang 2016 IEEE International Solid-State Circuits Conference (ISSCC), 308-309, 2016 | 59 | 2016 |
| Internal Node Jumper for Memory Bit Cells S Shridharan, Z Guo, EA Karl, G Shchupak, T Kosinovsky US Patent 11,205,616, 2021 | 55 | 2021 |
| A 0.6 V, 1.5 GHz 84 Mb SRAM in 14 nm FinFET CMOS technology with capacitive charge-sharing write assist circuitry E Karl, Z Guo, J Conary, J Miller, YG Ng, S Nalam, D Kim, J Keane, ... IEEE Journal of Solid-State Circuits 51 (1), 222-229, 2015 | 54 | 2015 |
David BlaauwProfessor of Electrical Engineering and Computer Science, University of MichiganEmail verificata su umich.edu