| A CMOS bandgap reference circuit with sub-1-V operation H Banba, H Shiga, A Umezawa, T Miyaba, T Tanzawa, S Atsumi, K Sakui IEEE Journal of Solid-State Circuits 34 (5), 670-674, 1999 | 1326 | 1999 |
| Non-volatile semiconductor memory device Y Itoh, K Sakui US Patent 6,107,658, 2000 | 163 | 2000 |
| A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory T Tanaka, Y Tanaka, H Nakamura, K Sakui, H Oodaira, R Shirota, ... IEEE Journal of Solid-State Circuits 29 (11), 1366-1373, 1994 | 162 | 1994 |
| Semiconductor memory having transistors connected in series K Sakui, M Noguchi US Patent 6,411,548, 2002 | 155 | 2002 |
| A new static memory cell based on reverse base current (RBC) effect of bipolar transistor K Sakui, T Hasegawa, T Fuse, S Watanabe, K Ohuchi, F Masuoka Technical Digest., International Electron Devices Meeting, 44-47, 1988 | 144 | 1988 |
| A new static memory cell based on the reverse base current effect of bipolar transistors K Sakui, T Hasegawa, T Fuse, S Watanabe, K Ohuchi, F Masuoka IEEE transactions on electron devices 36 (6), 1215-1217, 1989 | 139 | 1989 |
| Nonvolatile semiconductor memory, fabrication method for the same, semiconductor integrated circuits and systems M Ichige, K Hashimoto, T Kuji, S Mori, R Shirota, Y Takeuchi, K Sakui US Patent 6,845,042, 2005 | 138 | 2005 |
| Multichip semiconductor device and memory card K Sakui, J Miyamoto, N Hayasaka, K Okumura US Patent 6,239,495, 2001 | 130 | 2001 |
| Non-volatile semiconductor memory device Y Itoh, K Sakui US Patent 6,011,287, 2000 | 128 | 2000 |
| Non-volatile semiconductor memory device K Sakui, H Nakamura US Patent 6,295,227, 2001 | 125 | 2001 |
| Nonvolatile memory with active and passive wear leveling K Sakui, K Suzuki, D Yoshioka, K Kamimura, T Ishimoto, J Sumino US Patent 7,694,066, 2010 | 120 | 2010 |
| A new technique for measuring threshold voltage distribution in flash EEPROM devices T Himeno, N Matsukawa, H Hazama, K Sakui, M Oshikiri, K Masuda, ... Proceedings International Conference on Microelectronic Test Structures, 283-287, 1995 | 109 | 1995 |
| A reliable bi-polarity write/erase technology in flash EEPROMs S Aritome, R Shirota, R Kirisawa, T Endoh, R Nakayama, K Sakui, ... International Technical Digest on Electron Devices, 111-114, 1990 | 108 | 1990 |
| Nonvolatile semiconductor memory K Sakui, J Miyamoto US Patent 6,307,807, 2001 | 107 | 2001 |
| Nonvolatile semiconductor memory device whose addresses are selected in a multiple access K Sakui, K Tokushige, K Imamiya US Patent 6,097,666, 2000 | 102 | 2000 |
| Stacked type semiconductor device M Matsuo, N Hayasaka, T Arikado, H Ishiuchi, K Sakui, C Takubo US Patent 6,717,251, 2004 | 101 | 2004 |
| A 120-mm/sup 2/64-Mb NAND flash memory achieving 180 ns/Byte effective program speed JK Kim, K Sakui, SS Lee, Y Itoh, SC Kwon, K Kanazawa, KJ Lee, ... IEEE Journal of Solid-State Circuits 32 (5), 670-680, 1997 | 98 | 1997 |
| A 2.3 mu m/sup 2/memory cell structure for 16 Mb NAND EEPROMs R Shirota, R Nakayama, R Kirisawa, M Momodomi, K Sakui, Y Itoh, ... International Technical Digest on Electron Devices, 103-106, 1990 | 91 | 1990 |
| Nonvolatile semiconductor memory device K Takeuchi, K Sakui, T Tanaka, S Aritome US Patent 6,046,940, 2000 | 87 | 2000 |
| Semiconductor memory device K Sakui, Y Itoh, Y Iwata US Patent 6,049,494, 2000 | 83 | 2000 |
