| Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET N Loubet, T Hook, P Montanini, CW Yeung, S Kanakasabapathy, ... 2017 symposium on VLSI technology, T230-T231, 2017 | 911 | 2017 |
| A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels R Xie, P Montanini, K Akarvardar, N Tripathi, B Haran, S Johnson, T Hook, ... 2016 IEEE international electron devices meeting (IEDM), 2.7. 1-2.7. 4, 2016 | 191 | 2016 |
| High performance 45-nm SOI technology with enhanced strain, porous low-k BEOL, and immersion lithography P Agnello, T Ivers, C Warm, R Wise, R Wachnik, D Schepis, S Sankaran, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 132 | 2006 |
| A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process X Chen, S Samavedam, V Narayanan, K Stein, C Hobbs, C Baiocco, W Li, ... 2008 symposium on vlsi technology, 88-89, 2008 | 130 | 2008 |
| A manufacturable dual channel (Si and SiGe) high-k metal gate CMOS technology with multiple oxides for high performance and low power applications S Krishnan, U Kwon, N Moumen, MW Stoker, ECT Harley, S Bedell, ... 2011 International Electron Devices Meeting, 28.1. 1-28.1. 4, 2011 | 128 | 2011 |
| High performance UTBB FDSOI devices featuring 20nm gate length for 14nm node and beyond Q Liu, M Vinet, J Gimbert, N Loubet, R Wacquez, L Grenouillet, Y Le Tiec, ... 2013 IEEE International Electron Devices Meeting, 9.2. 1-9.2. 4, 2013 | 123 | 2013 |
| High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET K Cheng, A Khakifirooz, N Loubet, S Luning, T Nagumo, M Vinet, Q Liu, ... 2012 International Electron Devices Meeting, 18.1. 1-18.1. 4, 2012 | 121 | 2012 |
| High-performance high-κ/metal gates for 45nm CMOS and beyond with gate-first processing M Chudzik, B Doris, R Mo, J Sleight, E Cartier, C Dewan, D Park, H Bu, ... 2007 IEEE symposium on VLSI technology, 194-195, 2007 | 121 | 2007 |
| The last silicon transistor: Nanosheet devices could be the final evolutionary step for Moore's Law P Ye, T Ernst, MV Khare IEEE spectrum 56 (8), 30-35, 2019 | 114 | 2019 |
| A 10nm platform technology for low power and high performance application featuring FINFET devices with multi workfunction gate stack on bulk and SOI KI Seo, B Haran, D Gupta, D Guo, T Standaert, R Xie, H Shang, E Alptekin, ... 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical …, 2014 | 111 | 2014 |
| Integration and optimization of embedded-SiGe, compressive and tensile stressed liner films, and stress memorization in advanced SOI CMOS technologies LT Su, J Pellerin, SF Huang, M Khare, D Schepis, K Rim, S Liming, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 96 | 2005 |
| 32nm general purpose bulk CMOS technology for high performance applications at low voltage F Arnaud, J Liu, YM Lee, KY Lim, S Kohler, J Chen, BK Moon, CW Lai, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 92 | 2008 |
| Channel doping impact on FinFETs for 22nm and beyond CH Lin, R Kambhampati, RJ Miller, TB Hook, A Bryant, W Haensch, ... 2012 Symposium on VLSI Technology (VLSIT), 15-16, 2012 | 88 | 2012 |
| Sub-25nm FinFET with advanced fin formation and short channel effect engineering T Yamashita, VS Basker, T Standaert, CC Yeh, T Yamamoto, K Maitra, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 14-15, 2011 | 76 | 2011 |
| Impact of back bias on ultra-thin body and BOX (UTBB) devices Q Liu, F Monsieur, A Kumar, T Yamamoto, A Yagishita, P Kulkarni, ... 2011 Symposium on VLSI Technology-Digest of Technical Papers, 160-161, 2011 | 70 | 2011 |
| High performance 65 nm SOI technology with enhanced transistor strain and advanced-low-K BEOL WH Lee, A Waite, H Nii, HM Nayfeh, V McGahay, H Nakayama, D Fried, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 4 …, 2005 | 70 | 2005 |
| Mechanism and process dependence of negative bias temperature instability (NBTI) for pMOSFETs with ultrathin gate dielectrics CH Liu, MT Lee, CY Lin, J Chen, K Schruefer, J Brighten, N Rovedo, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 70 | 2001 |
| FINFET technology featuring high mobility SiGe channel for 10nm and beyond D Guo, G Karve, G Tsutsui, KY Lim, R Robison, T Hook, R Vega, D Liu, ... 2016 IEEE Symposium on VLSI Technology, 1-2, 2016 | 68 | 2016 |
| Challenges and opportunities for high performance 32 nm CMOS technology JW Sleight, I Lauer, O Dokumaci, DM Fried, D Guo, B Haran, S Narasimha, ... 2006 International Electron Devices Meeting, 1-4, 2006 | 67 | 2006 |
| Scaling of 32nm low power SRAM with high-K metal gate HS Yang, R Wong, R Hasumi, Y Gao, NS Kim, DH Lee, S Badrudduza, ... 2008 IEEE International Electron Devices Meeting, 1-4, 2008 | 66 | 2008 |
