| A 3.2 Gbps/pin 8 Gbit 1.0 V LPDDR4 SDRAM with integrated ECC engine for sub-1 V DRAM core operation TY Oh, H Chung, JY Park, KW Lee, S Oh, SY Doo, HJ Kim, CY Lee, ... IEEE Journal of Solid-State Circuits 50 (1), 178-190, 2014 | 119 | 2014 |
| Memory system having multi-terminated multi-drop bus HJ Park, SJ Bae US Patent 7,274,583, 2007 | 99 | 2007 |
| An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 graphics DRAM with low power and low noise data bus inversion SJ Bae, KI Park, JD Ihm, HY Song, WJ Lee, HJ Kim, KH Kim, YS Park, ... IEEE journal of solid-state circuits 43 (1), 121-131, 2008 | 85 | 2008 |
| Majority voter circuits and semiconductor device including the same SJ Bae, JD Lim, GS Moon, KII Park US Patent App. 12/656,590, 2010 | 69 | 2010 |
| A 60nm 6Gb/s/pin GDDR5 graphics DRAM with multifaceted clocking and ISI/SSN-reduction techniques SJ Bae, YS Sohn, KI Park, KH Kim, DH Chung, JG Kim, SH Kim, MS Park, ... 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 61 | 2008 |
| A 16-Gb, 18-Gb/s/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking YJ Kim, HJ Kwon, SY Doo, M Ahn, YH Kim, YJ Lee, DS Kang, SG Do, ... IEEE Journal of Solid-State Circuits 54 (1), 197-209, 2018 | 59 | 2018 |
| A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation YS Sohn, SJ Bae, HJ Park, CH Kim, SI Cho Proceedings of the IEEE 2003 Custom Integrated Circuits Conference, 2003 …, 2003 | 54 | 2003 |
| Single ended pseudo differential interconnection circuit and single ended pseudo differential signaling method SJ Bae US Patent 7,868,790, 2011 | 53 | 2011 |
| On-die termination circuit, data output buffer and semiconductor memory device HS Seol, YS Sohn, DM Kim, JI Lee, KI Park, SJ Bae, S Kwak US Patent 8,531,898, 2013 | 47 | 2013 |
| Digital duty cycle correction circuit and method for multi-phase clock HJ Park, YC Jang, SJ Bae US Patent 6,958,639, 2005 | 44 | 2005 |
| AC-coupling phase interpolator and delay-locked loop using the same JG Kim, KII Park, SJ Bae, SH Kim, DH Chung US Patent 8,004,328, 2011 | 43 | 2011 |
| Latency control circuit and semiconductor memory device comprising same SH Kim, SJ Bae, HR Kim, HS Seol US Patent App. 13/743,412, 2013 | 41 | 2013 |
| A 3Gb/s 8b single-ended transceiver for 4-drop DRAM interface with digital calibration of equalization skew and offset coefficients SJ Bae, HJ Chi, HR Kim, HJ Park ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State …, 2005 | 41 | 2005 |
| A VCDL-based 60-760-MHz dual-loop DLL with infinite phase-shift capability and adaptive-bandwidth scheme SJ Bae, HJ Chi, YS Sohn, HJ Park IEEE journal of solid-state circuits 40 (5), 1119-1129, 2005 | 40 | 2005 |
| A 40nm 2Gb 7Gb/s/pin GDDR5 SDRAM with a programmable DQ ordering crosstalk equalizer and adjustable clock-tracking BW SJ Bae, YS Sohn, TY Oh, SH Kim, YS Yang, DH Kim, SH Kwak, HS Seol, ... 2011 IEEE international solid-state circuits conference, 498-500, 2011 | 39 | 2011 |
| Majority voter circuits and semiconductor devices including the same SJ Bae, JD Lim, GS Moon, KI Park US Patent 7,688,102, 2010 | 39 | 2010 |
| Data output buffer and memory device SH Kim, SJ Bae, JI Lee, KI Park US Patent 8,553,471, 2013 | 38 | 2013 |
| A single-loop SS-LMS algorithm with single-ended integrating DFE receiver for multi-drop DRAM interface HJ Chi, JS Lee, SH Jeon, SJ Bae, YS Sohn, JY Sim, HJ Park IEEE journal of solid-state circuits 46 (9), 2053-2063, 2011 | 38 | 2011 |
| 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme CK Lee, YJ Eom, JH Park, J Lee, HR Kim, K Kim, Y Choi, HJ Chang, J Kim, ... 2017 IEEE International Solid-State Circuits Conference (ISSCC), 390-391, 2017 | 36 | 2017 |
| Injection-locked phase locked loop circuits using delay locked loops JOO Hye-Yoon, SJ Bae, YS Sohn, H Song, IHM Jeong-Don US Patent 9,461,656, 2016 | 36 | 2016 |
Jae-Yoon SimPohang University of Science and TechnologyEmail verificata su postech.ac.kr
