| A near-threshold RISC-V core with DSP extensions for scalable IoT Endpoint Devices M Gautschi, PD Schiavone, A Traber, I Loi, A Pullini, D Rossi, E Flamand, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017 | 508 | 2017 |
| Slow and steady wins the race? A comparison of ultra-low-power RISC-V cores for Internet-of-Things applications PD Schiavone, F Conti, D Rossi, M Gautschi, A Pullini, E Flamand, ... 2017 27th International Symposium on Power and Timing Modeling, Optimization …, 2017 | 265 | 2017 |
| An IoT endpoint system-on-chip for secure and energy-efficient near-sensor analytics F Conti, R Schilling, PD Schiavone, A Pullini, D Rossi, FK Gürkaynak, ... IEEE Transactions on Circuits and Systems I: Regular Papers 64 (9), 2481-2494, 2017 | 159 | 2017 |
| PULP: A parallel ultra low power platform for next generation IoT applications D Rossi, F Conti, A Marongiu, A Pullini, I Loi, M Gautschi, G Tagliavini, ... 2015 IEEE Hot Chips 27 Symposium (HCS), 1-39, 2015 | 154 | 2015 |
| A 60 gops/w,− 1.8 v to 0.9 v body bias ulp cluster in 28 nm utbb fd-soi technology D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Bartolini, ... Solid-State Electronics 117, 170-184, 2016 | 79 | 2016 |
| Energy-efficient near-threshold parallel computing: The PULPv2 cluster D Rossi, A Pullini, I Loi, M Gautschi, FK Gürkaynak, A Teman, ... Ieee Micro 37 (5), 20-31, 2017 | 75 | 2017 |
| A 1Gbps LTE-advanced turbo-decoder ASIC in 65nm CMOS S Belfanti, C Roth, M Gautschi, C Benkeser, Q Huang 2013 Symposium on VLSI Circuits, C284-C285, 2013 | 70 | 2013 |
| Approximate 32-bit floating-point unit design with 53% power-area product reduction V Camus, J Schlachter, C Enz, M Gautschi, FK Gurkaynak ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, 465-468, 2016 | 54 | 2016 |
| 193 MOPS/mW@ 162 MOPS, 0.32 V to 1.15 V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing D Rossi, A Pullini, I Loi, M Gautschi, FK Gurkaynak, A Teman, ... 2016 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS XIX), 1-3, 2016 | 49 | 2016 |
| Tailoring instruction-set extensions for an ultra-low power tightly-coupled cluster of OpenRISC cores M Gautschi, A Traber, A Pullini, L Benini, M Scandale, A Di Federico, ... 2015 IFIP/IEEE International Conference on Very Large Scale Integration …, 2015 | 40 | 2015 |
| A heterogeneous multicore system on chip for energy efficient brain inspired computing A Pullini, F Conti, D Rossi, I Loi, M Gautschi, L Benini IEEE Transactions on Circuits and Systems II: Express Briefs 65 (8), 1094-1098, 2017 | 39 | 2017 |
| Customizing an open source processor to fit in an ultra-low power cluster with a shared L1 memory M Gautschi, D Rossi, L Benini Proceedings of the 24th edition of the great lakes symposium on VLSI, 87-88, 2014 | 31 | 2014 |
| 4.6 A 65nm CMOS 6.4-to-29.2 pJ/FLOP@ 0.8 V shared logarithmic floating point unit for acceleration of nonlinear function kernels in a tightly coupled processor cluster M Gautschi, M Schaffner, FK Gürkaynak, L Benini 2016 IEEE International Solid-State Circuits Conference (ISSCC), 82-83, 2016 | 30 | 2016 |
| PULPino: datasheet A Traber, M Gautschi ETH Zurich, University of Bologna 36, 2017 | 27 | 2017 |
| Exploring multi-banked shared-L1 program cache on ultra-low power, tightly coupled processor clusters I Loi, D Rossi, G Haugou, M Gautschi, L Benini Proceedings of the 12th ACM International Conference on Computing Frontiers, 1-8, 2015 | 27 | 2015 |
| RI5CY: User manual A Traber, M Gautschi, PD Schiavone Micrel Lab and Multitherman Lab University of Bologna: Bologna Italy, 2019 | 26 | 2019 |
| A− 1.8 V to 0.9 V body bias, 60 GOPS/W 4-core cluster in low-power 28nm UTBB FD-SOI technology D Rossi, A Pullini, M Gautschi, I Loi, FK Gurkaynak, P Flatresse, L Benini 2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference …, 2015 | 24 | 2015 |
| SIR10US: A tightly coupled elliptic-curve cryptography co-processor for the OpenRISC M Gautschi, M Muehlberghuber, A Traber, S Stucki, M Baer, R Andri, ... 2014 IEEE 25th International Conference on Application-Specific Systems …, 2014 | 18 | 2014 |
| A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision A Pullini, F Conti, D Rossi, I Loi, M Gautschi, L Benini 2016 IEEE International symposium on circuits and systems (ISCAS), 2910-2910, 2016 | 17 | 2016 |
| An extended shared logarithmic unit for nonlinear function kernel acceleration in a 65-nm CMOS multicore cluster M Gautschi, M Schaffner, FK Gürkaynak, L Benini IEEE Journal of Solid-State Circuits 52 (1), 98-112, 2016 | 16 | 2016 |
Luca BeniniETH Zürich, Università di BolognaEmail verificata su unibo.it
