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| Open-loop correction of duty-cycle error and quadrature phase error S Chandrasekaran, GS Srinivas US Patent 9,444,442, 2016 | 32 | 2016 |
| Receiver clock test circuitry and related methods and apparatuses S Chandrasekaran, K Desai US Patent 9,071,407, 2015 | 28 | 2015 |
| Reduction of current mismatch in PLL charge pump HMS Fazeel, L Raghavan, C Srinivasaraman, M Jain 2009 IEEE Computer Society Annual Symposium on VLSI, 7-12, 2009 | 23 | 2009 |
| Reference voltage generation in a single-ended receiver S Chandrasekaran US Patent 8,923,442, 2014 | 17 | 2014 |
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| Receiver clock test circuitry and related methods and apparatuses S Chandrasekaran, K Desai US Patent 9,537,617, 2017 | 5 | 2017 |
| Receiver clock test circuitry and related methods and apparatuses S Chandrasekaran, K Desai US Patent 9,906,335, 2018 | 2 | 2018 |
| Self-calibrating equalizer for optimal jitter performance using on-chip eye monitoring S Chandrasekaran, K Desai, A Sendhil, W Ng 2011 24th Internatioal Conference on VLSI Design, 6-11, 2011 | 1 | 2011 |
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| At-speed I/O Test for Fast Vref Optimization in High Speed Single-ended Memory Systems S Mukherjee, S Chandrasekaran, GS EK, A Sendhil 2013 26th International Conference on VLSI Design and 2013 12th …, 2013 | | 2013 |
