Direct tunneling current model for circuit simulation CH Choi, KH Oh, JS Goo, Z Yu, RW Dutton International Electron Devices Meeting 1999. Technical Digest (Cat. No …, 1999 | 70 | 1999 |
Analysis of nonuniform ESD current distribution in deep submicron NMOS transistors KH Oh, C Duvvury, K Banerjee, RW Dutton IEEE Transactions on Electron Devices 49 (12), 2171-2182, 2002 | 67 | 2002 |
A simulation study on novel field stop IGBTs using superjunction KH Oh, J Lee, KH Lee, YC Kim, C Yun IEEE transactions on electron devices 53 (4), 884-890, 2006 | 53 | 2006 |
Charge balance insulated gate bipolar transistor J Yedinak, K Oh, C Yun, J Lee US Patent App. 11/408,812, 2007 | 44 | 2007 |
Experimental investigation of 650V superjunction IGBTs KH Oh, J Kim, H Seo, J Jung, E Kim, SS Kim, C Yun 2016 28th International Symposium on Power Semiconductor Devices and ICs …, 2016 | 38 | 2016 |
Non-uniform bipolar conduction in single finger NMOS transistors and implications for deep submicron ESD design KH Oh, C Duvvury, C Salling, K Banerjee, RW Dutton 2001 IEEE International Reliability Physics Symposium Proceedings. 39th …, 2001 | 34 | 2001 |
New power MOSFET employing segmented trench body contact for improving the avalanche energy IH Ji, KH Cho, MK Han, SC Lee, SS Kim, KH Oh, CM Yun 2008 20th International Symposium on Power Semiconductor Devices and IC's …, 2008 | 26 | 2008 |
Guidelines for the power constrained design of a CMOS tuned LNA JS Goo, KH Oh, CH Choi, Z Yu, TH Lee, RW Dutton 2000 International Conference on Simulation Semiconductor Processes and …, 2000 | 26 | 2000 |
Investigation of short-circuit failure limited by dynamic-avalanche capability in 600-V punchthrough IGBTs KH Oh, YC Kim, KH Lee, CM Yun IEEE Transactions on Device and Materials Reliability 6 (1), 2-8, 2006 | 24 | 2006 |
Investigation of ESD performance in advanced CMOS technology KH Oh Stanford University, 2003 | 22 | 2003 |
Impact of gate-to-contact spacing on ESD performance of salicided deep submicron NMOS transistors KH Oh, C Duvvury, K Banerjee, RW Dutton IEEE Transactions on Electron Devices 49 (12), 2183-2192, 2002 | 22 | 2002 |
Investigation of gate to contact spacing effect on ESD robustness of salicided deep submicron single finger NMOS transistors KH Oh, C Duvvury, K Banerjee, RW Dutton 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th …, 2002 | 22 | 2002 |
Power semiconductor device using silicon substrate as field stop layer and method of manufacturing the same CM Yun, KH Oh, KH Lee, Y Kim US Patent 7,645,659, 2010 | 19 | 2010 |
Analysis of gate-bias-induced heating effects in deep-submicron ESD protection designs KH Oh, C Duvvury, K Banerjee, RW Dutton IEEE transactions on device and materials reliability 2 (2), 36-42, 2002 | 17 | 2002 |
Gate bias induced heating effect and implications for the design of deep submicron ESD protection KH Oh, C Duvvury, K Banerjee, RW Dutton International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 17 | 2001 |
Geometry-controllable design blocks of MOS transistors for improved ESD protection C Duvvury, KH Oh US Patent 6,833,568, 2004 | 16 | 2004 |
Modeling of temperature dependent contact resistance for analysis of ESD reliability KH Oh, JH Chun, K Banerjee, C Duvvury, RW Dutton 2003 IEEE International Reliability Physics Symposium Proceedings, 2003 …, 2003 | 16 | 2003 |
650V superjunction MOSFET using universal charge balance concept through drift region SC Lee, KH Oh, SS Kim, CM Yun 2014 IEEE 26th International Symposium on Power Semiconductor Devices & IC's …, 2014 | 14 | 2014 |
Non-uniform conduction induced reverse channel length dependence of ESD reliability for silicided NMOS transistors KH Oh, K Banerjee, C Duvvury, RW Dutton Digest. International Electron Devices Meeting,, 341-344, 2002 | 14 | 2002 |
Wide bandgap device in parallel with a device that has a lower avalanche breakdown voltage and a higher forward voltage drop than the wide bandgap device JA Yedinak, RL Woodin, CL Rexer, PM Shenoy, K Oh, C Yun US Patent 7,586,156, 2009 | 13* | 2009 |