| Mode-level vs. implementation-level physical security in symmetric cryptography: a practical guide through the leakage-resistance jungle D Bellizia, O Bronchain, G Cassiers, V Grosso, C Guo, C Momin, ... Advances in Cryptology–CRYPTO 2020: 40th Annual International Cryptology …, 2020 | 87 | 2020 |
| Spook: Sponge-based leakage-resistant authenticated encryption with a masked tweakable block cipher D Bellizia, F Berti, O Bronchain, G Cassiers, S Duval, C Guo, G Leander, ... IACR Transactions on Symmetric Cryptology 2020 (S1), 295--349, 2020 | 81 | 2020 |
| A systematic appraisal of side channel evaluation strategies M Azouaoui, D Bellizia, I Buhan, N Debande, S Duval, C Giraud, ... Security Standardisation Research: 6th International Conference, SSR 2020 …, 2020 | 57 | 2020 |
| A novel ultra-compact FPGA-compatible TRNG architecture exploiting latched ring oscillators R Della Sala, D Bellizia, G Scotti IEEE Transactions on Circuits and Systems II: Express Briefs 69 (3), 1672-1676, 2021 | 49 | 2021 |
| Design of low-voltage high-speed CML D-latches in nanometer CMOS technologies G Scotti, D Bellizia, A Trifiletti, G Palumbo IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (12 …, 2017 | 44 | 2017 |
| Reducing a masked Implementation’s effective security order with setup manipulations: And an explanation based on externally-amplified couplings I Levi, D Bellizia, FX Standaert IACR Transactions on Cryptographic Hardware and Embedded Systems, 293-317, 2019 | 42 | 2019 |
| Secure double rate registers as an RTL countermeasure against power analysis attacks D Bellizia, S Bongiovanni, P Monsurrò, G Scotti, A Trifiletti, FB Trotta IEEE transactions on very large scale integration (vlsi) systems 26 (7 …, 2018 | 42 | 2018 |
| Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications D Bellizia, S Bongiovanni, P Monsurrò, G Scotti, A Trifiletti IEEE transactions on Emerging topics in Computing 5 (3), 329-339, 2016 | 32 | 2016 |
| High-throughput FPGA-compatible TRNG architecture exploiting multistimuli metastable cells R Della Sala, D Bellizia, G Scotti IEEE Transactions on Circuits and Systems I: Regular Papers 69 (12), 4886-4897, 2022 | 31 | 2022 |
| A lightweight FPGA compatible weak-PUF primitive based on XOR gates R Della Sala, D Bellizia, G Scotti IEEE Transactions on Circuits and Systems II: Express Briefs 69 (6), 2972-2976, 2022 | 30 | 2022 |
| A novel ultra-compact fpga puf: The dd-puf R Della Sala, D Bellizia, G Scotti Cryptography 5 (3), 23, 2021 | 30 | 2021 |
| Ask less, get more: Side-channel signal hiding, revisited I Levi, D Bellizia, D Bol, FX Standaert IEEE Transactions on Circuits and Systems I: Regular Papers 67 (12), 4904-4917, 2020 | 30 | 2020 |
| SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing D Bellizia, S Bongiovanni, M Olivieri, G Scotti IEEE Transactions on Circuits and Systems I: Regular Papers, 1-14, 2020 | 29 | 2020 |
| TEL logic style as a countermeasure against side-channel attacks: Secure cells library in 65nm CMOS and experimental results D Bellizia, G Scotti, A Trifiletti IEEE Transactions on Circuits and Systems I: Regular Papers 65 (11), 3874-3884, 2018 | 26 | 2018 |
| Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to side channel attacks exploiting static power D Bellizia, G Scotti, A Trifiletti 2016 MIXDES-23rd International Conference Mixed Design of Integrated …, 2016 | 25 | 2016 |
| Template attacks exploiting static power and application to CMOS lightweight crypto‐hardware D Bellizia, M Djukanovic, G Scotti, A Trifiletti International Journal of Circuit Theory and Applications 45 (2), 229-241, 2017 | 18 | 2017 |
| Novel measurements setup for attacks exploiting static power using DC pico-ammeter D Bellizia, D Cellucci, V Di Stefano, G Scotti, A Trifiletti 2017 European Conference on Circuit Theory and Design (ECCTD), 1-4, 2017 | 15 | 2017 |
| Post-quantum cryptography: Challenges and opportunities for robust and secure HW design D Bellizia, N El Mrabet, AP Fournaris, S Pontié, F Regazzoni, ... 2021 IEEE International Symposium on Defect and fault tolerance in VLSI and …, 2021 | 14 | 2021 |
| Beyond algorithmic noise or how to shuffle parallel implementations? I Levi, D Bellizia, FX Standaert International Journal of Circuit Theory and Applications 48 (5), 674-695, 2020 | 14 | 2020 |
| Multivariate analysis exploiting static power on nanoscale CMOS circuits for cryptographic applications M Djukanovic, D Bellizia, G Scotti, A Trifiletti Progress in Cryptology-AFRICACRYPT 2017: 9th International Conference on …, 2017 | 14 | 2017 |
Giuseppe ScottiSapienza Università di RomaEmail verificata su uniroma1.it