| Dynamic reconfiguration of embedded-DRAM caches employing zero data detection based refresh optimisation SS Manohar, HK Kapoor Journal of Systems Architecture 100, 101648, 2019 | 8 | 2019 |
| CAPMIG: Coherence-aware block placement and migration in multiretention STT-RAM caches SS Manohar, HK Kapoor IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 5 | 2022 |
| Towards optimizing refresh energy in embedded-DRAM caches using private blocks SS Manohar, S Agarwal, HK Kapoor Proceedings of the 2019 on Great Lakes Symposium on VLSI, 225-230, 2019 | 3 | 2019 |
| Refresh optimised embedded-dram caches based on zero data detection SS Manohar, HK Kapoor Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 635-642, 2019 | 3 | 2019 |
| CORIDOR: Using COherence and TempoRal LocalIty to Mitigate Read Disurbance ErrOR in STT-RAM Caches SS Manohar, S Mittal, HK Kapoor ACM Transactions on Embedded Computing Systems (TECS) 21 (1), 1-24, 2022 | 2 | 2022 |