| A linear threshold gate implementation in single electron technology C Lageweg, S Cotofana, S Vassiliadis Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging …, 2001 | 149 | 2001 |
| Single electron encoded latches and flip-flops C Lageweg, S Cotofana, S Vassiliadis IEEE Transactions on Nanotechnology 3 (2), 237-248, 2004 | 90 | 2004 |
| Addition related arithmetic operations via controlled transport of charge S Cotofana, C Lageweg, S Vassiliadis IEEE Transactions on Computers 54 (3), 243-256, 2005 | 72 | 2005 |
| Static buffered set based logic gates C Lageweg, S Cotofana, S Vassiliadis Nanotechnology, 2002. IEEE-NANO 2002. Proceedings of the 2002 2nd IEEE …, 2002 | 56 | 2002 |
| A full adder implementation using SET based linear threshold gates C Lageweg, S Cotofana, S Vassiliadis Electronics, Circuits and Systems, 2002. 9th International Conference on 2 …, 2002 | 47 | 2002 |
| Digital to analog conversion performed in single electron technology C Lageweg, S Cotofana, S Vassiliadis Proceedings of the 2001 1st IEEE Conference on Nanotechnology. IEEE-NANO …, 2001 | 25 | 2001 |
| Multi-target Data Aggregation and Tracking in Wireless Sensor Networks. M Ditzel, C Lageweg, J Janssen, A Theil J. Networks 3 (1), 1-9, 2008 | 20 | 2008 |
| Binary addition based on single electron tunneling devices C Lageweg, S Cotofana, S Vassiliadis 4th IEEE Conference on Nanotechnology, 2004., 327-330, 2004 | 20 | 2004 |
| First experiences with Personal Networks as an enabling platform for service providers FTH den Hartog, MA Blom, CR Lageweg, ME Peeters, JR Schmidt, ... 2007 Fourth Annual International Conference on Mobile and Ubiquitous Systems …, 2007 | 19 | 2007 |
| Single electron tunneling based arithmetic computation CR Lageweg Delft University of Technology, Netherlands, 2004 | 17 | 2004 |
| Achieving Fanout capabilities in single electron encoded logic networks C Lageweg, S Cotofana, S Vassiliadis Solid-State and Integrated-Circuit Technology, 2001. Proceedings. 6th …, 2001 | 16 | 2001 |
| Designing an automatic schematic generator for a netlist description CR Lageweg Delft University of Technology, Delft, Netherlands, Tech. Rep, 1998 | 14 | 1998 |
| Evaluation methodology for single electron encoded threshold logic gates C Lageweg, S Cotofana, S Vassiliadis VLSI-SOC: From Systems to Chips, 247-262, 2006 | 13 | 2006 |
| On computing addition related arithmetic operations via controlled transport of charge S Cotofana, C Lageweg, S Vassiliadis Proceedings 2003 16th IEEE Symposium on Computer Arithmetic, 245-252, 2003 | 13 | 2003 |
| Binary multiplication based on single electron tunneling C Lageweg, S Cotofana, S Vassiliadis Proceedings. 15th IEEE International Conference on Application-Specific …, 2004 | 9 | 2004 |
| Single electron encoded logic memory elements C Lageweg, S Cotofana, S Vassiliadis Nanotechnology, 2003. IEEE-NANO 2003. 2003 Third IEEE Conference on 1, 449 …, 2003 | 7 | 2003 |
| Data aggregation for target tracking in wireless sensor networks C Lageweg, J Janssen, M Ditzel European Conference on Smart Sensing and Context, 15-24, 2006 | 6 | 2006 |
| Buffer design trade-offs for single electron logic gates C Lageweg, S Cotofana, S Vassiliadis Nanotechnology, 2005. 5th IEEE Conference on, 279-282 vol. 1, 2005 | 6 | 2005 |
| Design methodology for single electron based building blocks C Meenderinck, C Lageweg, S Cotofana Nanotechnology, 2005. 5th IEEE Conference on, 117-120 vol. 1, 2005 | 5 | 2005 |
| High radix addition via conditional charge transport in single electron tunneling technology C Meenderinck, S Cotofana, C Lageweg 2005 IEEE International Conference on Application-Specific Systems …, 2005 | 4 | 2005 |
Sorin CotofanaQuantum & Computer Engineering, Delft University of TechnologyEmail verificata su tudelft.nl