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Srimanta Baishya
Srimanta Baishya
Email verificata su nits.ac.in
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Citata da
Citata da
Anno
Temperature effect on RF/analog and linearity parameters in DMG FinFET
R Saha, B Bhowmick, S Baishya
Applied Physics A 124, 1-10, 2018
902018
Comparative analysis of the quantum FinFET and trigate FinFET based on modeling and simulation
NP Maity, R Maity, S Maity, S Baishya
Journal of Computational Electronics 18, 492-499, 2019
712019
A modified capacitance model of RF MEMS shunt switch incorporating fringing field effects of perforated beam
K Guha, M Kumar, S Agarwal, S Baishya
Solid-State Electronics 114, 35-42, 2015
572015
A tunneling current density model for ultra thin HfO2 high-k dielectric material based MOS devices
NP Maity, R Maity, RK Thapa, S Baishya
Superlattices and Microstructures 95, 24-32, 2016
562016
Voltage and oxide thickness dependent tunneling current density and tunnel resistivity model: application to high-k material HfO2 based MOS devices
NP Maity, R Maity, S Baishya
Superlattices and Microstructures 111, 628-641, 2017
552017
Heterojunction fully depleted SOI-TFET with oxide/source overlap
S Chander, B Bhowmick, S Baishya
Superlattices and Microstructures 86, 43-50, 2015
542015
Electrical noise in circular gate tunnel FET in presence of interface traps
R Goswami, B Bhowmick, S Baishya
Superlattices and Microstructures 86, 342-354, 2015
522015
Effect of scaling on noise in circular gate TFET and its application as a digital inverter
R Goswami, B Bhowmick, S Baishya
Microelectronics Journal 53, 16-24, 2016
492016
A subthreshold surface potential model for short-channel MOSFET taking into account the varying depth of channel depletion layer due to source and drain junctions
S Baishya, A Mallik, CK Sarkar
IEEE transactions on electron devices 53 (3), 507-514, 2006
482006
A two-dimensional gate threshold voltage model for a heterojunction SOI-tunnel FET with oxide/source overlap
S Chander, S Baishya
IEEE Electron device letters 36 (7), 714-716, 2015
472015
Study of Interface Charge Densities for ZrO2 and HfO2 Based Metal‐Oxide‐Semiconductor Devices
NP Maity, R Maity, RK Thapa, S Baishya
Advances in Materials Science and Engineering 2014 (1), 497274, 2014
472014
Impact of thin high-k dielectrics and gate metals on RF characteristics of 3D double gate junctionless transistor
A Baidya, S Baishya, TR Lenka
Materials Science in Semiconductor Processing 71, 413-420, 2017
442017
Tri-gate heterojunction SOI Ge-FinFETs
R Das, R Goswami, S Baishya
Superlattices and Microstructures 91, 51-61, 2016
422016
Two-dimensional analytical modeling for electrical characteristics of Ge/Si SOI-tunnel FinFETs
S Chander, S Baishya, SK Sinha, S Kumar, PK Singh, K Baral, ...
Superlattices and Microstructures 131, 30-39, 2019
402019
Performance analysis of RF MEMS capacitive switch with non uniform meandering technique
K Guha, M Kumar, A Parmar, S Baishya
Microsystem Technologies 22, 2633-2640, 2016
402016
Statistical dependence of gate metal work function on various electrical parameters for an n-channel Si step-FinFET
R Saha, B Bhowmick, S Baishya
IEEE Transactions on Electron Devices 64 (3), 969-976, 2017
382017
A model for doubly clamped piezoelectric energy harvesters with segmented electrodes
R Kashyap, TR Lenka, S Baishya
IEEE Electron Device Letters 36 (12), 1369-1372, 2015
382015
A hybrid memory-based dragonfly algorithm with differential evolution for engineering application
S Debnath, S Baishya, D Sen, W Arif
Engineering with Computers 37 (4), 2775-2802, 2021
362021
An analytical model for the surface potential and threshold voltage of a double-gate heterojunction tunnel FinFET
NP Maity, R Maity, S Baishya
Journal of computational electronics 18, 65-75, 2019
362019
Modeling, Simulation and Analysis of Surface Potential and Threshold Voltage: Application to High-K Material HfO2 Based FinFET
S Panchanan, R Maity, S Baishya, NP Maity
Silicon 13, 3271-3289, 2021
352021
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