| 10×10nm2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation B Govoreanu, GS Kar, YY Chen, V Paraschiv, S Kubicek, A Fantini, ... 2011 International Electron Devices Meeting, 31.6. 1-31.6. 4, 2011 | 914 | 2011 |
| Planar Bulk MOSFETs Versus FinFETs: An Analog/RF Perspective V Subramanian, B Parvais, J Borremans, A Mercha, D Linten, P Wambacq, ... IEEE Transactions on Electron Devices 53 (12), 3071-3079, 2006 | 194 | 2006 |
| Vertically stacked gate-all-around Si nanowire CMOS transistors with dual work function metal gates H Mertens, R Ritzenthaler, A Chasin, T Schram, E Kunnen, A Hikavyy, ... 2016 IEEE International Electron Devices Meeting (IEDM), 19.7. 1-19.7. 4, 2016 | 165 | 2016 |
| Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession T Chiarella, L Witters, A Mercha, C Kerner, M Rakowski, C Ortolland, ... Solid-State Electronics 54 (9), 855-860, 2010 | 160 | 2010 |
| Deposition of HfO2 on germanium and the impact of surface pretreatments S Van Elshocht, B Brijs, M Caymax, T Conard, T Chiarella, S De Gendt, ... Applied physics letters 85 (17), 3824-3826, 2004 | 137 | 2004 |
| Analysis of leakage currents and impact on off-state power consumption for CMOS technology in the 100-nm regime WK Henson, N Yang, S Kubicek, EM Vogel, JJ Wortman, K De Meyer, ... IEEE Transactions on Electron Devices 47 (7), 1393-1400, 2000 | 136 | 2000 |
| Impact of MOSFET oxide breakdown on digital circuit operation and reliability B Kaczer, R Degraeve, G Groeseneken, M Rasras, S Kubicek, ... International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No …, 2000 | 111 | 2000 |
| Work function of Ni silicide phases on HfSiON and SiO/sub 2: NiSi, Ni/sub 2/Si, Ni/sub 31/Si/sub 12/, and Ni/sub 3/Si fully silicided gates JA Kittl, MA Pawlak, A Lauwers, C Demeurisse, K Opsomer, KG Anil, ... IEEE electron device letters 27 (1), 34-36, 2005 | 87 | 2005 |
| Device and circuit-level analog performance trade-offs: a comparative study of planar bulk FETs versus FinFETs V Subramaniana, B Parvais, J Borremans, A Mercha, D Linten, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 80 | 2005 |
| 1.5× 10− 9 Ωcm2 Contact resistivity on highly doped Si: P using Ge pre-amorphization and Ti silicidation H Yu, M Schaekers, E Rosseel, A Peter, JG Lee, WB Song, S Demuynck, ... 2015 IEEE International Electron Devices Meeting (IEDM), 21.7. 1-21.7. 4, 2015 | 70 | 2015 |
| Characterization of epitaxial Si: C: P and Si: P layers for source/drain formation in advanced bulk FinFETs E Rosseel, HB Profijt, AY Hikavyy, J Tolle, S Kubicek, G Mannaert, ... ECS Transactions 64 (6), 977, 2014 | 62 | 2014 |
| Limitations of shift-and-ratio based L/sub eff/extraction techniques for MOS transistors with halo or pocket implants H Van Meer, K Henson, JH Lyu, M Rosmeulen, S Kubicek, N Collaert, ... IEEE Electron Device Letters 21 (3), 133-136, 2000 | 59 | 2000 |
| 10× 10 nm 2 Hf/HfOx crossbar resistive RAM with excellent performance, reliability and low-energy operation. in 2011 Int B Govoreanu, GS Kar, YY Chen, V Paraschiv, S Kubicek, A Fantini, ... Electron Devices Meet 31, 1-31.6, 2011 | 56 | 2011 |
| Selective epitaxial growth of high-P Si: P for source/drain formation in advanced Si nFETs E Rosseel, SK Dhayalan, AY Hikavyy, R Loo, HB Profijt, D Kohen, ... ECS Transactions 75 (8), 347, 2016 | 55 | 2016 |
| Electrical characterisation of high-k materials prepared by atomic layer CVD RJ Carter, E Cartier, M Caymax, S De Gendt, R Degraevel, ... Extended Abstracts of International Workshop on Gate Insulator. IWGI 2001 …, 2001 | 54 | 2001 |
| A new technique to fabricate ultra-shallow-junctions, combining in situ vapour HCl etching and in situ doped epitaxial SiGe re-growth R Loo, M Caymax, P Meunier-Beillard, I Peytier, F Holsteyns, S Kubicek, ... Applied surface science 224 (1-4), 63-67, 2004 | 53 | 2004 |
| Demonstration of fully Ni-silicided metal gates on HfO/sub 2/based high-k gate dielectrics as a candidate for low power applications KG Anil, A Veloso, S Kubicek, T Schram, E Augendre, JF de Marneffe, ... Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 190-191, 2004 | 49 | 2004 |
| IEDM Tech. Dig. B Govoreanu, GS Kar, Y Chen, V Paraschiv, S Kubicek, A Fantini IEDM Tech. Dig, 729, 2011 | 46 | 2011 |
| On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub 2/and poly-Si/TiN/HfSiON gate stacks R Singanamalla, HY Yu, G Pourtois, I Ferain, KG Anil, S Kubicek, ... IEEE electron device letters 27 (5), 332-334, 2006 | 43 | 2006 |
| Practical accuracy analysis of some existing effective channel length and series resistance extraction methods for MOSFET's S Biesemans, M Hendriks, S Kubicek, K De Meyer IEEE Transactions on Electron Devices 45 (6), 1310-1316, 1998 | 43 | 1998 |
