| Improving GPU performance via large warps and two-level warp scheduling V Narasiman, M Shebanow, CJ Lee, R Miftakhutdinov, O Mutlu, YN Patt Proceedings of the 44th Annual IEEE/ACM International Symposium on …, 2011 | 556 | 2011 |
| Single instruction stream parallelism is greater than two M Butler, TY Yeh, Y Patt, M Alsup, H Scales, M Shebanow ACM SIGARCH Computer Architecture News 19 (3), 276-286, 1991 | 280 | 1991 |
| HPS, a new microarchitecture: Rationale and introduction YN Patt, W Hwu, M Shebanow ACM SIGMICRO Newsletter 16 (4), 103-108, 1985 | 231 | 1985 |
| Hardware support for large atomic units in dynamically scheduled machines SW Melvin, MC Shebanow, YN Patt Proceedings of the 21st annual workshop on Microprogramming and …, 1988 | 154 | 1988 |
| Atomic memory operators in a parallel processor IA Buck, JR Nickolls, MC Shebanow, LS Nyland US Patent 7,627,723, 2009 | 138 | 2009 |
| Method and apparatus for error detection and correction in systems comprising floppy and/or hard disk drives MS Young, J Drew, MC Shebanow US Patent 4,667,326, 1987 | 123 | 1987 |
| Data processor for performing simultaneous instruction retirement and backtracking MC Shebanow, M Alsup US Patent 5,355,457, 1994 | 122 | 1994 |
| Processor structure and method for maintaining and restoring precise state at any instruction boundary GW Shen, J Szeto, NA Patkar, MC Shebanow US Patent 5,649,136, 1997 | 110 | 1997 |
| Critical issues regarding HPS, a high performance microarchitecture YN Patt, SW Melvin, W Hwu, MC Shebanow Proceedings of the 18th annual workshop on Microprogramming, 109-116, 1985 | 109 | 1985 |
| Processor structure and method for a time-out checkpoint GW Shen, J Szeto, NA Patkar, MC Shebanow US Patent 5,644,742, 1997 | 85 | 1997 |
| Method and apparatus for register management using issue sequence prior physical register and register association validity information MC Shebanow, GW Shen, R Swami, NA Patkar US Patent 5,675,759, 1997 | 68 | 1997 |
| Method and apparatus for transferring data between a disk and a central processing unit MS Young, J Drew, MC Shebanow US Patent 4,667,286, 1987 | 65 | 1987 |
| Processor structure and method for renamable trap-stack MC Shebanow, H Osone US Patent 5,673,408, 1997 | 62 | 1997 |
| Trap handler architecture for a parallel processing unit MC Shebanow, J Choquette, BW Coon, SJ Heinrich, A Kalaiah, ... US Patent 8,522,000, 2013 | 59 | 2013 |
| Superscalar processor with multiple register windows and speculative return address generation A Katsuno, SW Savkar, MC Shebanow US Patent 5,896,528, 1999 | 56 | 1999 |
| Processor structure and method for tracking instruction status to maintain precise state GW Shen, J Szeto, NA Patkar, MC Shebanow US Patent 5,751,985, 1998 | 55 | 1998 |
| Processor structure and method for aggressively scheduling long latency instructions including load/store instructions while maintaining precise state GW Shen, J Szeto, NA Patkar, MC Shebanow, MA Simone US Patent 5,651,124, 1997 | 52 | 1997 |
| Randomly accessible memory having time overlapping memory accesses MC Shebanow, MK Alsup, HL Scales, GP Hoekstra US Patent 5,367,494, 1994 | 52 | 1994 |
| Processor structure and method for checkpointing instructions to maintain precise state GW Shen, J Szeto, NA Patkar, MC Shebanow US Patent 5,659,721, 1997 | 50 | 1997 |
| Processor structure and method for tracking floating-point exceptions GW Shen, J Szeto, MC Shebanow US Patent 5,673,426, 1997 | 42 | 1997 |