| Design and Implementation of a Standard Cell Library for Building Asynchronous ASICS MT Moreira Revista da Graduação 4 (1), 2011 | 91 | 2011 |
| Blade--a timing violation resilient asynchronous template D Hand, MT Moreira, HH Huang, D Chen, F Butzke, Z Li, M Gibiluka, ... 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems …, 2015 | 76 | 2015 |
| Return-to-one protocol for reducing static power in C-elements of QDI circuits employing m-of-n codes MT Moreira, RA Guazzelli, NLV Calazans 2012 25th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2012 | 53 | 2012 |
| Impact of C-elements in asynchronous circuits M Moreira, B Oliveira, F Moraes, N Calazans Thirteenth International Symposium on Quality Electronic Design (ISQED), 437-343, 2012 | 52 | 2012 |
| A 65nm standard cell set and flow dedicated to automated asynchronous circuits design M Moreira, B Oliveira, J Pontes, N Calazans 2011 IEEE International SOC Conference, 99-104, 2011 | 46 | 2011 |
| Hermes-glp: A gals network on chip router with power control techniques J Pontes, M Moreira, R Soares, N Calazans 2008 IEEE Computer Society Annual Symposium on VLSI, 347-352, 2008 | 44 | 2008 |
| Hermes-AA: A 65nm asynchronous NoC router with adaptive routing JJH Pontes, MT Moreira, FG Moraes, NLV Calazans 23rd IEEE International SOC Conference, 493-498, 2010 | 34 | 2010 |
| Semi-custom NCL design with commercial EDA frameworks: Is it possible? M Moreira, A Neutzling, M Martins, A Reis, R Ribas, N Calazans 2014 20th IEEE International Symposium on Asynchronous Circuits and Systems …, 2014 | 33 | 2014 |
| Hermes-A–an asynchronous NoC router with distributed routing J Pontes, M Moreira, F Moraes, N Calazans Integrated Circuit and System Design. Power and Timing Modeling …, 2011 | 31 | 2011 |
| Adapting a C-element design flow for low power M Moreira, B Oliveira, J Pontes, F Moraes, N Calazans 2011 18th IEEE International Conference on Electronics, Circuits, and …, 2011 | 30 | 2011 |
| Automatic layout synthesis with ASTRAN applied to asynchronous cells A Ziesemer, R Reis, MT Moreira, ME Arendt, NLV Calazans 2014 IEEE 5th Latin American Symposium on Circuits and Systems, 1-4, 2014 | 28 | 2014 |
| Ncl+: Return-to-one null convention logic MT Moreira, CHM Oliveira, RC Porto, NLV Calazans 2013 IEEE 56th International Midwest Symposium on Circuits and Systems …, 2013 | 27 | 2013 |
| A bundled-data asynchronous circuit synthesis flow using a commercial EDA framework M Gibiluka, MT Moreira, NLV Calazans 2015 Euromicro Conference on Digital System Design, 79-86, 2015 | 26 | 2015 |
| Design of NCL gates with the ASCEnD flow MT Moreira, CHM Oliveira, RC Porto, NLV Calazans 2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS), 1-4, 2013 | 25 | 2013 |
| Analysis and optimization of programmable delay elements for 2-phase bundled-data circuits G Heck, LS Heck, A Singhvi, MT Moreira, PA Beerel, NLV Calazans 2015 28th international conference on VLSI design, 321-326, 2015 | 24 | 2015 |
| Read your circuit: leveraging word embedding to guide logic optimization WL Neto, MT Moreira, L Amaru, C Yu, PE Gaillardon Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 22 | 2021 |
| Lichen: Automated electrical characterization of asynchronous standard cell libraries MT Moreira, CHM Oliveira, NLV Calazans, LC Ost 2013 Euromicro Conference on Digital System Design, 933-940, 2013 | 22 | 2013 |
| SLAP: A supervised learning approach for priority cuts technology mapping WL Neto, MT Moreira, Y Li, L Amarù, C Yu, PE Gaillardon 2021 58th ACM/IEEE Design Automation Conference (DAC), 859-864, 2021 | 21 | 2021 |
| NCL synthesis with conventional EDA tools: Technology mapping and optimization MT Moreira, PA Beerel, MLL Sartori, NLV Calazans IEEE Transactions on Circuits and Systems I: Regular Papers 65 (6), 1981-1993, 2017 | 21 | 2017 |
| Automated synthesis of cell libraries for asynchronous circuits M Trevisan, M Arendt, A Ziesemer, R Reis, NLV Calazans Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 1-7, 2014 | 21 | 2014 |
Ney Laert Vilar CalazansInvited Researcher at the Graduate Program on Microelectronics (PGMICRO), UFRGSEmail verificata su inf.ufrgs.br