| DIANA: An end-to-end energy-efficient digital and ANAlog hybrid neural network SoC K Ueyoshi, IA Papistas, P Houshmand, GM Sarda, V Jain, M Shi, Q Zheng, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 69 | 2022 |
| Artificial Neural Network Based on Doped HfO2 Ferroelectric Capacitors With Multilevel Characteristics Q Zheng, Z Wang, N Gong, Z Yu, C Chen, Y Cai, Q Huang, H Jiang, Q Xia, ... IEEE Electron Device Letters 40 (8), 1309-1312, 2019 | 65 | 2019 |
| Diana: An end-to-end hybrid digital and analog neural network soc for the edge P Houshmand, GM Sarda, V Jain, K Ueyoshi, IA Papistas, M Shi, Q Zheng, ... IEEE Journal of Solid-State Circuits 58 (1), 203-215, 2022 | 47 | 2022 |
| Lattice: An ADC/DAC-less ReRAM-based processing-in-memory architecture for accelerating deep convolution neural networks Q Zheng, Z Wang, Z Feng, B Yan, Y Cai, R Huang, Y Chen, CL Yang, ... 2020 57th ACM/IEEE Design Automation Conference (DAC), 1-6, 2020 | 44 | 2020 |
| Self-activation neural network based on self-selective memory device with rectified multilevel states Z Wang, Q Zheng, J Kang, Z Yu, G Zhong, Y Ling, L Bao, S Bao, G Bai, ... IEEE Transactions on Electron Devices 67 (10), 4166-4171, 2020 | 30 | 2020 |
| MobiLatice: a depth-wise DCNN accelerator with hybrid digital/analog nonvolatile processing-in-memory block Q Zheng, X Li, Z Wang, G Sun, Y Cai, R Huang, Y Chen, H Li Proceedings of the 39th International Conference on Computer-Aided Design, 1-9, 2020 | 23 | 2020 |
| Processing-in-memory technology for machine learning: From basic to asic B Taylor, Q Zheng, Z Li, S Li, Y Chen IEEE Transactions on Circuits and Systems II: Express Briefs 69 (6), 2598-2603, 2022 | 11 | 2022 |
| PIMulator-NN: An event-driven, cross-level simulation framework for processing-in-memory-based neural network accelerators Q Zheng, X Li, Y Guan, Z Wang, Y Cai, Y Chen, G Sun, R Huang IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 8 | 2022 |
| ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapses Z Li, Q Zheng, B Yan, R Huang, B Li, Y Chen Proceedings of the 59th ACM/IEEE Design Automation Conference, 1099-1104, 2022 | 7 | 2022 |
| A RRAM based max-pooling scheme for convolutional neural network Y Ling, Z Wang, Y Yang, Z Yu, Q Zheng, Y Qin, Y Cai, R Huang 2021 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), 1-3, 2021 | 7 | 2021 |
| EMS-i: An Efficient Memory System Design with Specialized Caching Mechanism for Recommendation Inference Y Wang, S Li, Q Zheng, A Chang, H Li, Y Chen ACM Transactions on Embedded Computing Systems 22 (5s), 1-22, 2023 | 6 | 2023 |
| Accelerating Sparse Attention with a Reconfigurable Non-volatile Processing-In-Memory Architecture Q Zheng, S Li, Y Wang, Z Li, Y Chen, HH Li 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 6 | 2023 |
| Sida: Sparsity-inspired data-aware serving for efficient and scalable large mixture-of-experts models Z Du, S Li, Y Wu, X Jiang, J Sun, Q Zheng, Y Wu, A Li, H Li, Y Chen Proceedings of Machine Learning and Systems 6, 224-238, 2024 | 5 | 2024 |
| Enhance the robustness to time dependent variability of ReRAM-based neuromorphic computing systems with regularization and 2R synapse Q Zheng, J Kang, Z Wang, Y Cai, R Huang, B Li, Y Chen, H Li 2019 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2019 | 5 | 2019 |
| SpikeSen: Low-Latency In-Sensor-Intelligence Design With Neuromorphic Spiking Neurons Z Li, Q Zheng, Y Chen, H Li IEEE Transactions on Circuits and Systems II: Express Briefs 70 (6), 1876-1880, 2023 | 4 | 2023 |
| Improving the robustness and efficiency of PIM-based architecture by SW/HW co-design X Yang, S Li, Q Zheng, Y Chen Proceedings of the 28th Asia and South Pacific Design Automation Conference …, 2023 | 3 | 2023 |
| In-Storage Acceleration of Graph-Traversal-Based Approximate Nearest Neighbor Search Y Wang, S Li, Q Zheng, L Song, Z Li, A Chang, H Li, Y Chen arXiv preprint arXiv:2312.03141, 2023 | 2 | 2023 |
| Apparatus and method for matrix multiplication using processing-in-memory Q Zheng US Patent 11,797,643, 2023 | 2 | 2023 |
| NDSEARCH: Accelerating Graph-Traversal-Based Approximate Nearest Neighbor Search through Near Data Processing Y Wang, S Li, Q Zheng, L Song, Z Li, A Chang, Y Chen 2024 ACM/IEEE 51st Annual International Symposium on Computer Architecture …, 2024 | 1 | 2024 |
| Block-Wise Mixed-Precision Quantization: Enabling High Efficiency for Practical ReRAM-based DNN Accelerators X Wu, E Hanson, N Wang, Q Zheng, X Yang, H Yang, S Li, F Cheng, ... arXiv preprint arXiv:2310.12182, 2023 | 1 | 2023 |
Yiran ChenJohn Cocke Distinguished Professor of Electrical and Computer Engineering, Duke UniversityEmail verificata su duke.edu