| VLSI test principles and architectures: design for testability LT Wang, CW Wu, X Wen Elsevier, 2006 | 986 | 2006 |
| RRAM defect modeling and failure analysis based on march test and a novel squeeze-search scheme CY Chen, HC Shih, CW Wu, CH Lin, PF Chiu, SS Sheu, FT Chen IEEE Transactions on Computers 64 (1), 180-190, 2014 | 260 | 2014 |
| Built-in redundancy analysis for memory yield improvement CT Huang, CF Wu, JF Li, CW Wu IEEE transactions on Reliability 52 (4), 386-399, 2003 | 248 | 2003 |
| On-chip TSV testing for 3D IC before bonding using sense amplification PY Chen, CW Wu, DM Kwai 2009 Asian Test Symposium, 450-455, 2009 | 180 | 2009 |
| A programmable BIST core for embedded DRAM CT Huang, JR Huang, CF Wu, CW Wu, TY Chang IEEE Design & Test of Computers 16 (1), 59-70, 1999 | 161 | 1999 |
| On-chip testing of blind and open-sleeve TSVs for 3D IC before bonding PY Chen, CW Wu, DM Kwai 2010 28th VLSI Test Symposium (VTS), 263-268, 2010 | 153 | 2010 |
| A built-in self-repair design for RAMs with 2-D redundancy JF Li, JC Yeh, RF Huang, CW Wu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13 (6), 742-745, 2005 | 133 | 2005 |
| A high-throughput low-cost AES processor CP Su, TF Lin, CT Huang, CW Wu IEEE Communications Magazine 41 (12), 86-91, 2003 | 133 | 2003 |
| Efficient built-in redundancy analysis for embedded memories with 2-D redundancy SK Lu, YC Tsai, CH Hsu, KH Wang, CW Wu IEEE Transactions on Very Large Scale Integration (VLSI) Systems 14 (1), 34-42, 2006 | 130 | 2006 |
| Single-and multi-core configurable AES architectures for flexible security MY Wang, CP Su, CL Horng, CW Wu, CT Huang IEEE Transactions on Very Large Scale Integration (VLSI) Systems 18 (4), 541-552, 2009 | 112 | 2009 |
| IEEE Std. 1149.1 boundary scan circuit capable of built-in self-testing CH Tsai, FD Guo, JH Hong, CW Wu US Patent 5,570,375, 1996 | 111 | 1996 |
| RAMSES: a fast memory fault simulator CF Wu, CT Huang, CW Wu Proceedings 1999 IEEE International Symposium on Defect and Fault Tolerance …, 1999 | 107 | 1999 |
| An adaptive-rate error correction scheme for NAND flash memory TH Chen, YY Hsiao, YT Hsing, CW Wu 2009 27th IEEE VLSI Test Symposium, 53-58, 2009 | 99 | 2009 |
| An integrated ECC and redundancy repair scheme for memory reliability enhancement CL Su, YT Yeh, CW Wu 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005 | 98 | 2005 |
| March-based RAM diagnosis algorithms for stuck-at and coupling faults JF Li, KL Cheng, CT Huang, CW Wu Proceedings International Test Conference 2001 (Cat. No. 01CH37260), 758-767, 2001 | 96 | 2001 |
| A built-in self-test scheme for the post-bond test of TSVs in 3D ICs YJ Huang, JF Li, JJ Chen, DM Kwai, YF Chou, CW Wu 29th VLSI test symposium, 20-25, 2011 | 92 | 2011 |
| A built-in self-repair scheme for semiconductor memories with 2-D redundancy JF Li, JC Yeh, RF Huang, CW Wu, PY Tsai, A Hsu, E Chow International Test Conference, 2003. Proceedings. ITC 2003., 393-393, 2003 | 92 | 2003 |
| RSA cryptosystem design based on the Chinese remainder theorem CH Wu, JH Hong, CW Wu Proceedings of the 2001 Asia and South Pacific Design automation conference …, 2001 | 92 | 2001 |
| Sequential circuit fault simulation using logic emulation SA Hwang, JH Hong, CW Wu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1998 | 90 | 1998 |
| An HMAC processor with integrated SHA-1 and MD5 algorithms MY Wang, CP Su, CT Huang, CW Wu ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE …, 2004 | 83 | 2004 |
Jin-Fu LiDepartment of Electrical Engineering, National Central UniversityEmail verificata su ee.ncu.edu.tw
