| Digital Communication Receivers: Synchronization, Channel Estimation, and Signal Processing H Meyr, M Moeneclaey, SA Fechtel Digital Communication Receivers: Synchronization, Channel Estimation, and …, 1998 | 2448 | 1998 |
| Optimum receiver design for wireless broad-band systems using OFDM. I M Speth, SA Fechtel, G Fock, H Meyr IEEE Transactions on communications 47 (11), 1668-1677, 1999 | 1248 | 1999 |
| Digital filter and square timing recovery M Oerder, H Meyr IEEE Transactions on communications 36 (5), 605-612, 1988 | 857 | 1988 |
| Synchronization in Digital Communications H Meyr Wiley, 1990 | 663 | 1990 |
| Optimum receiver design for OFDM-based broadband transmission. II. A case study M Speth, S Fechtel, G Fock, H Meyr IEEE Transactions on communications 49 (4), 571-578, 2001 | 648 | 2001 |
| Frequency synchronization algorithms for OFDM systems suitable for communication over frequency selective fading channels F Classen, H Meyr Proceedings of IEEE Vehicular Technology Conference (VTC), 1655-1659, 1994 | 483 | 1994 |
| Frame synchronization of OFDM systems in frequency selective fading channels M Speth, F Classen, H Meyr 1997 IEEE 47th Vehicular Technology Conference. Technology in Motion 3, 1807 …, 1997 | 390 | 1997 |
| LISA—machine description language for cycle-accurate models of programmable DSP architectures S Pees, A Hoffmann, V Zivojnovic, H Meyr Proceedings of the 36th Annual ACM/IEEE Design Automation Conference, 933-938, 1999 | 342 | 1999 |
| A universal technique for fast and flexible instruction-set architecture simulation A Nohl, G Braun, O Schliebusch, R Leupers, H Meyr, A Hoffmann Proceedings of the 39th annual Design Automation Conference, 22-27, 2002 | 268 | 2002 |
| Architecture exploration for embedded processors with LISA A Hoffmann, H Meyr, R Leupers Kluwer Academic Publishers, 2002 | 246 | 2002 |
| High-speed parallel Viterbi decoding: Algorithm and VLSI-architecture G Fettweis, H Meyr IEEE Communications Magazine 29 (5), 46-55, 1991 | 242 | 1991 |
| A novel methodology for the design of application-specific instruction-set processors (ASIPs) using a machine description language A Hoffmann, T Kogel, A Nohl, G Braun, O Schliebusch, O Wahlen, ... IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2001 | 231 | 2001 |
| Parallel Viterbi algorithm implementation: Breaking the ACS-bottleneck G Fettweis, H Meyr IEEE Transactions on Communications 37 (8), 785-790, 1989 | 231 | 1989 |
| FRIDGE: a fixed-point design and simulation environment H Keding, M Willems, M Coors, H Meyr Proceedings Design, Automation and Test in Europe, 429-435, 1998 | 222 | 1998 |
| LISA-machine description language and generic machine model for HW/SW co-design V Zivojnovic, S Pees, H Meyr VLSI Signal Processing, IX, 127-136, 1996 | 207 | 1996 |
| Achievable rate of MIMO channels with data-aided channel estimation and perfect interleaving J Baltersee, G Fock, H Meyr IEEE Journal on Selected Areas in Communications 19 (12), 2358-2368, 2001 | 180 | 2001 |
| MAPS: an integrated framework for MPSoC application parallelization J Ceng, J Castrillón, W Sheng, H Scharwächter, R Leupers, G Ascheid, ... Proceedings of the 45th annual Design Automation Conference, 754-759, 2008 | 177 | 2008 |
| A systematic approach to carrier recovery and detection of digitally phase modulated signals of fading channels R Haeb, H Meyr IEEE Transactions on Communications 37 (7), 748-754, 1989 | 174 | 1989 |
| High-rate Viterbi processor: A systolic array solution G Fettweis, H Meyr IEEE Journal on Selected Areas in Communications 8 (8), 1520-1534, 1990 | 151 | 1990 |
| Optimum vectorization of scalable synchronous dataflow graphs S Ritz, M Pankert, V Zivojinovic, H Meyr Proceedings of International Conference on Application Specific Array …, 1993 | 141 | 1993 |
Gerhard P. FettweisVodafone Chair Professor, TU Dresden / Barkhausen Institut, DresdenEmail verificata su tu-dresden.de