Ikuti
David Bol
Judul
Dikutip oleh
Dikutip oleh
Tahun
A 0.086-mm 12.7-pJ/SOP 64k-Synapse 256-Neuron Online-Learning Digital Spiking Neuromorphic Processor in 28-nm CMOS
C Frenkel, M Lefebvre, JD Legat, D Bol
IEEE transactions on biomedical circuits and systems 13 (1), 145-158, 2018
4272018
Interests and limitations of technology scaling for subthreshold logic
D Bol, R Ambroise, D Flandre, JD Legat
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 17 (10 …, 2009
2112009
SleepWalker: A 25-MHz 0.4-V Sub-mm² 7µW/MHz Microcontroller in 65-nm LP/GP CMOS for Low-Carbon Wireless Sensor Nodes
D Bol, J De Vos, C Hocquet, F Botman, F Durvaux, S Boyd, D Flandre, ...
IEEE Journal of Solid-State Circuits 48 (1), 20-32, 2013
183*2013
MorphIC: A 65-nm 738k-Synapse/mm Quad-Core Binary-Weight Digital Neuromorphic Processor With Stochastic Spike-Driven Online Learning
C Frenkel, JD Legat, D Bol
IEEE transactions on biomedical circuits and systems 13 (5), 999-1010, 2019
1692019
Towards green cryptography: a comparison of lightweight ciphers from the energy viewpoint
S Kerckhof, F Durvaux, C Hocquet, D Bol, FX Standaert
International Workshop on Cryptographic Hardware and Embedded Systems, 390-407, 2012
1302012
Learning without feedback: Fixed random learning signals allow for feedforward training of deep neural networks
C Frenkel, M Lefebvre, D Bol
Frontiers in neuroscience 15, 629892, 2021
972021
Assessing the embodied carbon footprint of IoT edge devices with a bottom-up life-cycle approach
T Pirson, D Bol
Journal of Cleaner Production 322, 128966, 2021
872021
SleepTalker: A ULV 802.15. 4a IR-UWB transmitter SoC in 28-nm FDSOI achieving 14 pJ/b at 27 Mb/s with channel selection based on adaptive FBB and digitally programmable pulse …
G de Streel, F Stas, T Gurne, F Durant, C Frenkel, A Cathelin, D Bol
IEEE Journal of Solid-State Circuits 52 (4), 1163-1177, 2017
772017
Analysis, modeling, and design of a 2.45-GHz RF energy harvester for SWIPT IoT smart sensors
P Xu, D Flandre, D Bol
IEEE Journal of Solid-State Circuits 54 (10), 2717-2729, 2019
752019
Green SoCs for a sustainable Internet-of-Things
D Bol, J De Vos, F Botman, G de Streel, S Bernard, D Flandre, JD Legat
2013 IEEE Faible Tension Faible Consommation, 1-4, 2013
712013
7.7 A 0.2-to-3.6 TOPS/W programmable convolutional imager SoC with in-sensor current-domain ternary-weighted MAC operations for feature extraction and region-of-interest detection
M Lefebvre, L Moreau, R Dekimpe, D Bol
2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 118-120, 2021
652021
Analysis and minimization of practical energy in 45nm subthreshold logic circuits
D Bol, R Ambroise, D Flandre, JD Legat
2008 IEEE International Conference on Computer Design, 294-300, 2008
652008
Bottom-up and top-down neural processing systems design: Neuromorphic intelligence as the convergence of natural and artificial intelligence
CP Frenkel, D Bol, G Indiveri
ArXiv. org, 2021
632021
Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits
D Bol, D Flandre, JD Legat
Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009
632009
Bottom-up and top-down approaches for the design of neuromorphic processing systems: Tradeoffs and synergies between natural and artificial intelligence
C Frenkel, D Bol, G Indiveri
Proceedings of the IEEE 111 (6), 623-652, 2023
612023
A low-complexity LoRa synchronization algorithm robust to sampling time offsets
M Xhonneux, O Afisiadis, D Bol, J Louveaux
IEEE Internet of Things Journal 9 (5), 3756-3769, 2021
602021
A 25MHz 7μW/MHz ultra-low-voltage microcontroller SoC in 65nm LP/GP CMOS for low-carbon wireless sensor nodes
D Bol, J De Vos, C Hocquet, F Botman, F Durvaux, S Boyd, D Flandre, ...
2012 IEEE International Solid-State Circuits Conference, 490-492, 2012
572012
A 28-nm convolutional neuromorphic processor enabling online learning with spike-based retinas
C Frenkel, JD Legat, D Bol
2020 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2020
552020
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
D Bol, D Kamel, D Flandre, JD Legat
Proceedings of the 2009 ACM/IEEE international symposium on Low power …, 2009
552009
8.4 a 0.33 v/-40 c process/temperature closed-loop compensation soc embedding all-digital clock multiplier and dc-dc converter exploiting fdsoi 28nm back-gate biasing
S Clerc, M Saligane, F Abouzeid, M Cochet, JM Daveau, C Bottoni, D Bol, ...
2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015
542015
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