| Vitruvius+: an area-efficient RISC-V decoupled vector coprocessor for high performance computing applications F Minervini, O Palomar, O Unsal, E Reggiani, J Quiroga, J Marimon, ... ACM Transactions on Architecture and Code Optimization 20 (2), 1-25, 2023 | 46 | 2023 |
| On how to improve fpga-based systems design productivity via sdaccel G Guidi, E Reggiani, L Di Tucci, G Durelli, M Blott, MD Santambrogio 2016 IEEE international parallel and distributed processing symposium …, 2016 | 39 | 2016 |
| Pareto optimal design space exploration for accelerated CNN on FPGA E Reggiani, M Rabozzi, AM Nestorov, A Scolari, L Stornaiuolo, ... 2019 IEEE International Parallel and Distributed Processing Symposium …, 2019 | 22 | 2019 |
| Mix-GEMM: An efficient HW-SW architecture for mixed-precision quantized deep neural networks inference on edge devices E Reggiani, A Pappalardo, M Doblas, M Moreto, M Olivieri, OS Unsal, ... 2023 IEEE International Symposium on High-Performance Computer Architecture …, 2023 | 19 | 2023 |
| Enhancing the scalability of multi-fpga stencil computations via highly optimized hdl components E Reggiani, E Del Sozzo, D Conficconi, G Natale, C Moroni, ... ACM Transactions on Reconfigurable Technology and Systems (TRETS) 14 (3), 1-33, 2021 | 19 | 2021 |
| Bison-e: A lightweight and high-performance accelerator for narrow integer linear algebra computing on the edge E Reggiani, CR Lazo, RF Bagué, A Cristal, M Olivieri, OS Unsal Proceedings of the 27th ACM International Conference on Architectural …, 2022 | 14 | 2022 |
| From exaflop to exaflow T Becker, P Burovskiy, AM Nestorov, H Palikareva, E Reggiani, ... Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 …, 2017 | 11 | 2017 |
| Adaptable register file organization for vector processors CR Lazo, E Reggiani, CR Morales, RF Bagué, LAV Vargas, MAR Salinas, ... 2022 IEEE International Symposium on High-Performance Computer Architecture …, 2022 | 10 | 2022 |
| Pearson Correlation Coefficient acceleration for modeling and mapping of neural interconnections E Reggiani, E D’Arnese, A Purgato, MD Santambrogio 2017 IEEE International Parallel and Distributed Processing Symposium …, 2017 | 10 | 2017 |
| A scalable dataflow implementation of Curran's approximation algorithm AM Nestorov, E Reggiani, H Palikareva, P Burovskiy, T Becker, ... 2017 IEEE international parallel and distributed processing symposium …, 2017 | 10 | 2017 |
| Flex-sfu: Accelerating dnn activation functions by non-uniform piecewise approximation E Reggiani, R Andri, L Cavigelli 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 9 | 2023 |
| DVINO: A RISC-V vector processor implemented in 65nm technology G Cabo, G Candón, X Carril, M Doblas, M Domínguez, A González, ... 2022 37th Conference on Design of Circuits and Integrated Circuits (DCIS), 1-6, 2022 | 9 | 2022 |
| Performance portable fpga design N Voss, T Becker, S Tilbury, G Gaydadjiev, O Mencer, AM Nestorov, ... Proceedings of the 2020 ACM/SIGDA International Symposium on Field …, 2020 | 6 | 2020 |
| An FPGA-based acceleration methodology and performance model for iterative stencils E Reggiani, G Natale, C Moroni, MD Santambrogio 2018 IEEE International Parallel and Distributed Processing Symposium …, 2018 | 6 | 2018 |
| Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology M Doblas, G Candón, X Carril, M Domínguez, E Erra, A González, ... 2023 38th Conference on Design of Circuits and Integrated Systems (DCIS), 1-6, 2023 | 3 | 2023 |
| A case study for an accelerated dcnn on fpga-based embedded distributed system AM Nestorov, A Scolari, E Reggiani, L Stornaiuolo, MD Santambrogio 2019 IEEE International Parallel and Distributed Processing Symposium …, 2019 | 3 | 2019 |
| Mix-GEMM: Extending RISC-V CPUs for Energy-Efficient Mixed-Precision DNN Inference using Binary Segmentation J Fornt, E Reggiani, P Fontova-Musté, N Rodas, A Pappalardo, OS Unsal, ... IEEE Transactions on Computers, 2024 | | 2024 |
| Efficient hardware acceleration of deep neural networks via arithmetic complexity reduction E Reggiani Universitat Politècnica de Catalunya, 2023 | | 2023 |
| Sargantana: an academic SoC RISC-V processor in 22nm FDSOI technology M Doblas Font, G Candón Arenas, X Carril Gil, M Dominguez de la Rocha, ... 38th Conference on Design of Circuits and Integrated Systems (DCIS 2023 …, 2023 | | 2023 |
| DVINO: A RISC-V vector processor implemented in 65nm technology G Cabo Pitarch, G Candon, X Carril, M Doblas Font, ... DCIS 2022: proceedings of the 37th Conference on Design of Circuits and …, 2022 | | 2022 |