| FPGA implementations of BCD multipliers G Sutter, E Todorovich, G Bioul, M Vazquez, JP Deschamps 2009 International Conference on Reconfigurable Computing and FPGAs, 36-41, 2009 | 46 | 2009 |
| Decimal addition in FPGA G Bioul, M Vazquez, JP Deschamps, G Sutter 2009 5th Southern Conference on Programmable Logic (SPL), 101-108, 2009 | 27 | 2009 |
| Introducing programmable logic to undergraduate engineering students in a digital electronics course E Todorovich, JA Marone, M Vázquez IEEE Transactions on Education 55 (2), 255-262, 2011 | 22 | 2011 |
| Decimal adders/subtractors in FPGA: efficient 6-input LUT implementations M Vazquez, G Sutter, G Bioul, JP Deschamps 2009 International Conference on Reconfigurable Computing and FPGAs, 42-47, 2009 | 21 | 2009 |
| Real-time speckle image processing E Todorovich, AL Dai Pra, LI Passoni, M Vázquez, E Cozzolino, F Ferrara, ... Journal of Real-Time Image Processing 11, 535-545, 2016 | 15 | 2016 |
| High‐Speed FPGA 10′ s Complement Adders‐Subtractors G Bioul, M Vazquez, JP Deschamps, G Sutter International Journal of Reconfigurable Computing 2010 (1), 219764, 2010 | 8 | 2010 |
| FPGA based implementation of imagezero compression algorithm L Leiva, M Vázquez, M Tosini, O Goñi, J Noguera IEEE Latin America Transactions 18 (02), 344-350, 2020 | 7 | 2020 |
| FPGA-based accelerator for AI-toolbox reinforcement learning library L Leiva, J Torrents-Barrena, M Vázquez IEEE Embedded Systems Letters 15 (2), 113-116, 2022 | 5 | 2022 |
| FPGA-specific decimal sign-magnitude addition and subtraction M Vázquez, E Todorovich International Journal of Electronics 103 (7), 1166-1185, 2016 | 5 | 2016 |
| Metodologías de diseño para sistemas embebidos MA Tosini, E Todorovich, MO Vázquez, L Leiva, C Aciti, JA Marone, ... XV workshop de investigadores en ciencias de la computación, 2013 | 5 | 2013 |
| Herramienta de Generación de Arquitecturas Hardware para Reconocimiento de Patrones en Imágenes L Leiva, M Vázquez, N Acosta, G Sutter JCRA 2007: Jornadas de Computación Reconfigurable y Aplicaciones, 2007 | 5 | 2007 |
| Herramienta para diseño automático de arquitecturas a medida basadas en redes neuronales para reconocimiento de patrones visuales L Leiva, N Acosta, MO Vázquez VIII Workshop de Investigadores en Ciencias de la Computación, 2006 | 4 | 2006 |
| FPGA acceleration analysis of LibSVM predictors based on high-level synthesis L Leiva, M Vázquez, J Torrents-Barrena The Journal of Supercomputing 78 (12), 14137-14163, 2022 | 3 | 2022 |
| Radix-10 restoring square root for 6-input LUTs programmable devices M Vázquez, M Tosini, L Leiva Circuits, Systems, and Signal Processing 40, 2335-2360, 2021 | 3 | 2021 |
| Design and implementation of decimal fixed-point square root in lut-6 fpgas M Vázquez, M Tosini 2014 IX Southern Conference on Programmable Logic (SPL), 1-6, 2014 | 3 | 2014 |
| Experiences applying framework-based functional verification to a design for programmable logic O Goñi, M Vazquez, E Todorovich, G Sutter 2011 VII Southern Conference on Programmable Logic (SPL), 109-115, 2011 | 3 | 2011 |
| A FPGA IEEE-754-2008 decimal64 Floating-Point adder/subtractor C Minchola, M Vazquez, G Sutter 2011 VII Southern Conference on Programmable Logic (SPL), 251-256, 2011 | 3 | 2011 |
| Implementación en FPGA de algoritmo para análisis parasitario GI Rombolá, EL Leiva, M Vázquez, JM Toloza, MF Sagüés, CA Saumell Universidad de Buenos Aires. Facultad de Ingeniería, 2022 | 2 | 2022 |
| Técnicas de optimización de soluciones en sistemas embebidos MA Tosini, L Leiva, MO Vázquez, OE Goñi, JM Toloza XXIII Workshop de Investigadores en Ciencias de la Computación (WICC 2021 …, 2021 | 2 | 2021 |
| Radix-10 decimal logarithm by direct selection for 6-input luts programmable devices M Vázquez, L Leiva, G Sutter Microprocessors and Microsystems 64, 143-158, 2019 | 2 | 2019 |
